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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [c/] [rsp-rtl_sim.h] - Diff between revs 40 and 46

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Rev 40 Rev 46
Line 58... Line 58...
#endif
#endif
 
 
 
 
#define DBG_ON  0
#define DBG_ON  0
 
 
 
#define DBG_JP_VPI 0
 
 
#define DBG_VPI 0
#define DBG_VPI 0
 
 
extern int vpi_to_rsp_pipe[2]; // [0] - read, [1] - write
#define DBG_CALLS 0
extern int rsp_to_vpi_pipe[2]; // [0] - read, [1] - write
 
extern int command_pipe[2]; // RSP end writes, VPI end reads ONLY
extern uint32_t vpi_to_rsp_pipe[2]; // [0] - read, [1] - write
 
extern uint32_t rsp_to_vpi_pipe[2]; // [0] - read, [1] - write
 
extern uint32_t command_pipe[2]; // RSP end writes, VPI end reads ONLY
 
 
#if (DEBUG) || (DEBUG2)
#if (DEBUG) || (DEBUG2)
#define flush_debug() fflush(stdout)
#define flush_debug() fflush(stdout)
#else
#else
#define flush_debug()
#define flush_debug()
Line 87... Line 91...
/* read a word from wishbone */
/* read a word from wishbone */
int dbg_wb_read32(uint32_t adr, uint32_t *data);
int dbg_wb_read32(uint32_t adr, uint32_t *data);
 
 
/* write a word to wishbone */
/* write a word to wishbone */
int dbg_wb_write32(uint32_t adr, uint32_t data);
int dbg_wb_write32(uint32_t adr, uint32_t data);
 
int dbg_wb_write16(uint32_t adr, uint16_t data);
 
int dbg_wb_write8(uint32_t adr, uint8_t data);
 
 
/* read a block from wishbone */
/* read a block from wishbone */
int dbg_wb_read_block32(uint32_t adr, uint32_t *data, int len);
int dbg_wb_read_block32(uint32_t adr, uint32_t *data, int len);
 
 
/* write a block to wishbone */
/* write a block to wishbone */

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