URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [c/] [rsp-rtl_sim.h] - Diff between revs 46 and 49

Rev 46	Rev 49
Line 101...	Line 101...

`/* write a block to wishbone */`	`/* write a block to wishbone */`
`int dbg_wb_write_block32(uint32_t adr, uint32_t *data, int len);`	`int dbg_wb_write_block32(uint32_t adr, uint32_t *data, int len);`

`/* read a register from cpu */`	`/* read a register from cpu */`
`int dbg_cpu0_read(uint32_t adr, uint32_t *data);`	`int dbg_cpu0_read(uint32_t adr, uint32_t *data, uint32_t length);`

`/* read a register from cpu module */`	`/* read a register from cpu module */`
`int dbg_cpu0_read_ctrl(uint32_t adr, unsigned char *data);`	`int dbg_cpu0_read_ctrl(uint32_t adr, unsigned char *data);`

`/* write a cpu register */`	`/* write a cpu register */`
`int dbg_cpu0_write(uint32_t adr, uint32_t data);`	`int dbg_cpu0_write(uint32_t adr, uint32_t *data, uint32_t length);`

`/* write a cpu module register */`	`/* write a cpu module register */`
`int dbg_cpu0_write_ctrl(uint32_t adr, unsigned char data);`	`int dbg_cpu0_write_ctrl(uint32_t adr, unsigned char data);`

`/* send a message to the sim that the debugging client has disconnected */`	`/* send a message to the sim that the debugging client has disconnected */`