URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [c/] [rsp-rtl_sim.h] - Diff between revs 49 and 397

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Rev 49	Rev 397
Line 36...	Line 36...
`#ifndef _RSP_RTL_SIM_H_`	`#ifndef _RSP_RTL_SIM_H_`
`#define _RSP_RTL_SIM_H_`	`#define _RSP_RTL_SIM_H_`

`#include <stdint.h> // For uint32_t types`	`#include <stdint.h> // For uint32_t types`

`//#define DEBUG 1`	`#define DEBUG 0`
`//#define DEBUG2 1`	`#define DEBUG2 0`
	`#define DBG_ON 0`
	`#define DBG_JP_VPI 0`
	`#define DBG_VPI 0`
	`#define DBG_CALLS 0`


`#define Boolean int`	`#define Boolean int`
`#define false 0`	`#define false 0`
`#define true 1`	`#define true 1`

`#ifdef DEBUG`	`#if DEBUG==1`
`#define debug printf`	`#define debug printf`
`#else`	`#else`
`#define debug`	`#define debug`
`#endif`	`#endif`

`#ifdef DEBUG2`	`#if DEBUG2==1`
`#define debug2 printf`	`#define debug2 printf`
`#else`	`#else`
`#define debug2`	`#define debug2`
`#endif`	`#endif`


`#define DBG_ON 0`

`#define DBG_JP_VPI 0`

`#define DBG_VPI 0`

`#define DBG_CALLS 0`

`extern uint32_t vpi_to_rsp_pipe[2]; // [0] - read, [1] - write`	`extern uint32_t vpi_to_rsp_pipe[2]; // [0] - read, [1] - write`
`extern uint32_t rsp_to_vpi_pipe[2]; // [0] - read, [1] - write`	`extern uint32_t rsp_to_vpi_pipe[2]; // [0] - read, [1] - write`
`extern uint32_t command_pipe[2]; // RSP end writes, VPI end reads ONLY`	`extern uint32_t command_pipe[2]; // RSP end writes, VPI end reads ONLY`

`#if (DEBUG) \|\| (DEBUG2)`	`#if (DEBUG) \|\| (DEBUG2)`
Line 88...	Line 85...
`/* function to kick off this server */`	`/* function to kick off this server */`
`void run_rsp_server(int);`	`void run_rsp_server(int);`

`/* read a word from wishbone */`	`/* read a word from wishbone */`
`int dbg_wb_read32(uint32_t adr, uint32_t *data);`	`int dbg_wb_read32(uint32_t adr, uint32_t *data);`
	`int dbg_wb_read8(uint32_t adr, uint8_t* data);`

`/* write a word to wishbone */`	`/* write a word to wishbone */`
`int dbg_wb_write32(uint32_t adr, uint32_t data);`	`int dbg_wb_write32(uint32_t adr, uint32_t data);`
`int dbg_wb_write16(uint32_t adr, uint16_t data);`	`int dbg_wb_write16(uint32_t adr, uint16_t data);`
`int dbg_wb_write8(uint32_t adr, uint8_t data);`	`int dbg_wb_write8(uint32_t adr, uint8_t data);`

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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [c/] [rsp-rtl_sim.h] - Diff between revs 49 and 397