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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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`define CMD_WB_BLOCK_WR32 4'h9
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`define CMD_WB_BLOCK_WR32 4'h9
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`define CMD_WB_BLOCK_RD32 4'ha
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`define CMD_WB_BLOCK_RD32 4'ha
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`define CMD_RESET 4'hb
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`define CMD_RESET 4'hb
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`define CMD_READ_JTAG_ID 4'hc
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`define CMD_READ_JTAG_ID 4'hc
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`define CMD_GDB_DETACH 4'hd
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`define CMD_GDB_DETACH 4'hd
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`define CMD_WB_RD8 4'he /* Byte read is useful with a system with byte peripherals! */
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// commands:
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// commands:
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// 4'h1 jtag set instruction register (input: instruction value)
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// 4'h1 jtag set instruction register (input: instruction value)
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// 4'h2 set debug chain (dbg_set_command here) (input: chain value)
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// 4'h2 set debug chain (dbg_set_command here) (input: chain value)
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// 4'h3 cpu_ctrl_wr (input: ctrl value (2 bits))
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// 4'h3 cpu_ctrl_wr (input: ctrl value (2 bits))
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// 4'h4 cpu_ctrl_rd (output: ctrl value (2bits))
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// 4'h4 cpu_ctrl_rd (output: ctrl value (2bits))
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