OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [verilog/] [vpi_debug_module.v] - Diff between revs 49 and 397

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 49 Rev 397
Line 56... Line 56... 
   reg                  tms;
 
   reg                  tms;
 
   reg                  tck;
 
   reg                  tck;
 
   reg                  tdi;
 
   reg                  tdi;
 
 
 
 
 
   reg [31:0]            in_data_le, in_data_be;
 
   reg [31:0]            in_data_le, in_data_be;
 
 
 
   reg [31:0]            incoming_word;
 
   reg                  err;
 
   reg                  err;
 
   integer              i;
 
   integer              i;
 
 
 
 
 
   reg [31:0]            id;
 
   reg [31:0]            id;
 
   reg [31:0]            npc;
 
   reg [31:0]            npc;
Line 112... Line 113... 
        // Insert a #delay here because we need to
 
        // Insert a #delay here because we need to
 
        // wait until the PC isn't pointing to flash anymore
 
        // wait until the PC isn't pointing to flash anymore
 
        // (this is around 20k ns if the flash_crash boot code
 
        // (this is around 20k ns if the flash_crash boot code
 
        // is being booted from, else much bigger, around 10mil ns)
 
        // is being booted from, else much bigger, around 10mil ns)
 
 
 
 
 
        #200_000 main;
 
        #2_000 main;
 
 
 
 
 
     end
 
     end
 
 
 
 
 
   task main;
 
   task main;
 
      begin
 
      begin
Line 191... Line 192... 
             `CMD_CPU_CTRL_RD : // cpu CTRL read
 
             `CMD_CPU_CTRL_RD : // cpu CTRL read
 
               begin
 
               begin
 
 
 
 
 
                  debug_cpu_rd_ctrl(cpu_ctrl_val);
 
                  debug_cpu_rd_ctrl(cpu_ctrl_val);
 
 
 
 
 
                  $return_command_data(cpu_ctrl_val);
 
                  $return_command_data(4,cpu_ctrl_val);
 
 
 
 
 
               end
 
               end
 
 
 
 
 
             `CMD_CPU_WR_REG :
 
             `CMD_CPU_WR_REG :
 
               begin
 
               begin
Line 285... Line 286... 
 
 
 
 
                  $get_command_address(cmd_adr);
 
                  $get_command_address(cmd_adr);
 
 
 
 
 
                  wb_read_32(cmd_data, cmd_adr, 16'h3);
 
                  wb_read_32(cmd_data, cmd_adr, 16'h3);
 
 
 
 
 
                  $return_command_data(cmd_data);
 
                  $return_command_data(4,cmd_data);
 
 
 
 
 
 
 
               end
 
 
 
 
 
 
 
             `CMD_WB_RD8 :
 
 
 
               begin
 
 
 
 
 
 
 
                  $get_command_address(cmd_adr);
 
 
 
 
 
 
 
                  wb_read_8(cmd_data, cmd_adr, 16'h0);
 
 
 
 
 
 
 
                  $return_command_data(1,cmd_data);
 
 
 
 
 
               end
 
               end
 
 
 
 
 
             `CMD_WB_BLOCK_WR32 :
 
             `CMD_WB_BLOCK_WR32 :
 
               begin
 
               begin
Line 320... Line 332... 
              `CMD_READ_JTAG_ID :
 
              `CMD_READ_JTAG_ID :
 
                begin
 
                begin
 
 
 
 
 
                   read_id_code(id);
 
                   read_id_code(id);
 
 
 
 
 
                   $return_command_data(id);
 
                   $return_command_data(4,id);
 
 
 
 
 
                end
 
                end
 
 
 
 
 
              `CMD_GDB_DETACH :
 
              `CMD_GDB_DETACH :
 
                begin
 
                begin
 
 
 
 
 
                   $display("Debugging client disconnected. Finishing simulation");
 
                   $display("(%t)(%m)Debugging client disconnected. Finishing simulation", $time);
 
 
 
 
 
 
 
 
 
                   $finish();
 
                   $finish();
 
 
 
 
 
                end
 
                end
Line 692... Line 704... 
         debug_wishbone_go(1'b1, 1'b0);
 
         debug_wishbone_go(1'b1, 1'b0);
 
         data = data_storage[0];
 
         data = data_storage[0];
 
         if (length>3)
 
         if (length>3)
 
           $display("WARNING: Only first data word is stored for writting ( See module %m)");
 
           $display("WARNING: Only first data word is stored for writting ( See module %m)");
 
      end
 
      end
 
   endtask
 
   endtask // wb_read_32
 
 
 
 
 
 
 
   // 8-bit read from the wishbone
 
 
 
   task wb_read_8;
 
 
 
 
 
 
 
    output [31:0] data;
 
 
 
 
 
 
 
    input [`DBG_WB_ADR_LEN -1:0] addr;
 
 
 
    input [`DBG_WB_LEN_LEN -1:0] length;
 
 
 
 
 
 
 
      begin
 
 
 
         debug_wishbone_wr_comm(`DBG_WB_READ8, addr, length, 1'b0);
 
 
 
         last_wb_cmd = `DBG_WB_READ8;  last_wb_cmd_text = "DBG_WB_READ8";
 
 
 
         length_global = length + 1;
 
 
 
         debug_wishbone_go(1'b1, 1'b0);
 
 
 
         data = data_storage[0];
 
 
 
      end
 
 
 
   endtask // wb_read_8
 
 
 
 
 
 
 
 
 
 
 
 
 
   // block 32-bit read from the wishbone
 
   // block 32-bit read from the wishbone
 
   // assumes data will be stored into data_storage[]
 
   // assumes data will be stored into data_storage[]
 
   task wb_block_read_32;
 
   task wb_block_read_32;
Line 989... Line 1019... 
              for (i=0; i<(length_global<<3); i=i+1)
 
              for (i=0; i<(length_global<<3); i=i+1)
 
                begin
 
                begin
 
 
 
 
 
                   gen_clk(1);
 
                   gen_clk(1);
 
 
 
 
 
                   if (i[4:0] == 31)   // Latching data
 
                   if (i[2:0] == 7)   // Latching data
 
                     begin
 
                        incoming_word = {incoming_word[23:0],in_data_be[7:0]};
 
 
 
 
 
                        data_storage[word_pointer] = in_data_be;
 
                   if (i[4:0] == 31)
 
 
 
                     begin
 
 
 
                        data_storage[word_pointer] = incoming_word;
 
`ifdef DEBUG_INFO
 
`ifdef DEBUG_INFO
 
                        $display("\t\tin_data_be = 0x%x", in_data_be);
 
                        $display("\t\tin_data_be = 0x%x", incoming_word);
 
`endif
 
`endif
 
                        word_pointer = word_pointer + 1;
 
                        word_pointer = word_pointer + 1;
 
 
 
 
 
                     end
 
                     end
 
 
 
                end // for (i=0; i<(length_global<<3); i=i+1)
 
 
 
 
 
 
 
              // Copy in any leftovers
 
 
 
              if (length_global[1:0] != 0)
 
 
 
                begin
 
 
 
                   data_storage[word_pointer] = incoming_word;
 
 
 
`ifdef DEBUG_INFO
 
 
 
                   $display("\t\tin_data_be = 0x%x", incoming_word);
 
 
 
`endif
 
                end
 
                end
 
           end
 
           end
 
 
 
 
 
         for(i=`DBG_WB_STATUS_LEN -1; i>=0; i=i-1)
 
         for(i=`DBG_WB_STATUS_LEN -1; i>=0; i=i-1)
 
           begin
 
           begin

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.