| Line 17... |
Line 17... |
#
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#
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# Name of the directory we're currently in
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# Name of the directory we're currently in
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CUR_DIR=$(shell pwd)
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CUR_DIR=$(shell pwd)
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VENDOR=actel
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VENDOR_TCL_SHELL=acttclsh
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PROJECT_NAME=orpsoc
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PROJECT_TOP_NAME=$(PROJECT_NAME)_top
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PROJ_ADB_FILE_NAME=$(PROJECT_NAME).adb
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PROJ_ADB_FILE=$(PROJ_ADB_FILE_NAME)
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# The root path of the whole project
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# The root path of the whole project
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BOARD_DIR ?=$(CUR_DIR)/../../..
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BOARD_ROOT ?=$(CUR_DIR)/../../..
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PROJECT_ROOT=$(BOARD_DIR)/../../..
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include $(BOARD_ROOT)/Makefile.inc
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BOARD_RTL_PATH=$(BOARD_DIR)/rtl
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BOARD_RTL_VERILOG_PATH=$(BOARD_RTL_PATH)/verilog
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BOARD_RTL_VERILOG_INCLUDES=$(BOARD_RTL_VERILOG_PATH)/include
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PROJECT_VERILOG_DEFINES=$(BOARD_RTL_VERILOG_INCLUDES)/$(PROJECT_NAME)-defines.v
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SYN_PATH=$(BOARD_DIR)/syn/synplify
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VENDOR_TCL_SHELL=acttclsh
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SW_PATH=$(PROJECT_ROOT)/sw
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PAR_PATH=$(BOARD_DIR)/backend/par
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DESIGN_TOP_NAME=$(DESIGN_NAME)_top
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PAR_RUN_PATH=$(PAR_PATH)/run
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PROJ_ADB_FILE_NAME=$(DESIGN_NAME).adb
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PAR_OUT_PATH=$(PAR_PATH)/out
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PROJ_ADB_FILE=$(PROJ_ADB_FILE_NAME)
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# Required EDIF file names
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# Required EDIF file names
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EDIF_NAME=$(PROJECT_TOP_NAME).edn
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EDIF_NAME=$(DESIGN_TOP_NAME).edn
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PROJ_EDF_FILE=$(SYN_PATH)/out/$(EDIF_NAME)
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PROJ_EDF_FILE=$(BOARD_SYN_DIR)/out/$(EDIF_NAME)
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# TCL script names
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# TCL script names
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TCL_SCRIPT_START=start.tcl
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TCL_SCRIPT_START=start.tcl
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TCL_SCRIPT_COMPILE=compile.tcl
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TCL_SCRIPT_COMPILE=compile.tcl
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TCL_SCRIPT_PAR=par.tcl
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TCL_SCRIPT_PAR=par.tcl
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| Line 78... |
Line 63... |
# Set to 'on' to enable them
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# Set to 'on' to enable them
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PLACE_INCREMENTAL ?= off
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PLACE_INCREMENTAL ?= off
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ROUTE_INCREMENTAL ?= off
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ROUTE_INCREMENTAL ?= off
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PLACER_HIGH_EFFORT ?= off
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PLACER_HIGH_EFFORT ?= off
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PDC_FILE ?=$(PROJECT_NAME).pdc
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PDC_FILE ?=$(DESIGN_NAME).pdc
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SDC_FILE ?=$(PROJECT_NAME).sdc
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SDC_FILE ?=$(DESIGN_NAME).sdc
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DEFINES_FILE_CUTOFF=$(shell grep -n "end of included module defines" $(PROJECT_VERILOG_DEFINES) | cut -d ':' -f 1)
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#DEFINES_FILE_CUTOFF=$(shell grep -n "end of included module defines" $(PROJECT_VERILOG_DEFINES) | cut -d ':' -f 1)
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DESIGN_DEFINES=$(shell cat $(PROJECT_VERILOG_DEFINES) | sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g )
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#DESIGN_DEFINES=$(shell cat $(PROJECT_VERILOG_DEFINES) | sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g )
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# Rule to look at what defines are being extracted from main file
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# Rule to look at what defines are being extracted from main file
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print-defines:
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#print-defines:
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@echo; echo "\t### Design defines ###"; echo
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# @echo; echo "\t### Design defines ###"; echo
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@echo "\tParsing "$(PROJECT_VERILOG_DEFINES)" and exporting:"
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# @echo "\tParsing "$(PROJECT_VERILOG_DEFINES)" and exporting:"
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@echo $(DESIGN_DEFINES)
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# @echo $(DESIGN_DEFINES)
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# Rule to print out current config of current session
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# Rule to print out current config of current session
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print-config:
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print-config:
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@echo; echo "\t### PAR make configuration ###"; echo
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@echo; echo "\t### PAR make configuration ###"; echo
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@echo "\tFPGA_FAMILY="$(FPGA_FAMILY)
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@echo "\tFPGA_FAMILY="$(FPGA_FAMILY)
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| Line 107... |
Line 92... |
@echo "\tPLACER_HIGH_EFFORT="$(PLACER_HIGH_EFFORT)
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@echo "\tPLACER_HIGH_EFFORT="$(PLACER_HIGH_EFFORT)
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@echo
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@echo
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@echo "\tBackend pinout script:"
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@echo "\tBackend pinout script:"
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@echo "\tBOARD_CONFIG="$(BOARD_CONFIG)
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@echo "\tBOARD_CONFIG="$(BOARD_CONFIG)
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# Set V=1 when calling make to enable verbose output
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# mainly for debugging purposes.
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ifeq ($(V), 1)
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Q=
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else
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Q ?=@
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endif
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TIME_CMD=time -p
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TIME_CMD=time -p
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# Rule for everything from, potentially, synthesis up to PAR
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# Rule for everything from, potentially, synthesis up to PAR
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all: print-config print-defines create-compile-par-bitgen
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all: print-config print-defines create-compile-par-bitgen
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| Line 148... |
Line 124... |
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$(PROJ_ADB_FILE): $(PROJ_EDF_FILE) $(TCL_SCRIPT_START)
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$(PROJ_ADB_FILE): $(PROJ_EDF_FILE) $(TCL_SCRIPT_START)
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$(TIME_CMD) $(VENDOR_TCL_SHELL) $(TCL_SCRIPT_START)
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$(TIME_CMD) $(VENDOR_TCL_SHELL) $(TCL_SCRIPT_START)
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$(PROJ_EDF_FILE):
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$(PROJ_EDF_FILE):
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$(MAKE) -C $(SYN_PATH)/run all
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$(MAKE) -C $(BOARD_SYN_DIR)/run all
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create-compile: create compile
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create-compile: create compile
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clean:
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clean:
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rm -rf *.rpt *.log *~ *.tcl *.lok *.tmp *.dtf $(SDC_FILE) $(PDC_FILE) *.adb
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rm -rf *.rpt *.log *~ *.tcl *.lok *.tmp *.dtf $(SDC_FILE) $(PDC_FILE) *.adb
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clean-syn:
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clean-syn:
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$(MAKE) -C $(SYN_PATH)/run distclean
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$(MAKE) -C $(BOARD_SYN_DIR)/run distclean
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clean-sw:
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clean-sw:
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$(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo;
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$(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo;
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$(MAKE) -C $(SW_PATH)/lib distclean
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$(MAKE) -C $(COMMON_SW_DIR)/lib distclean
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distclean: clean-sw clean-syn clean
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distclean: clean-sw clean-syn clean
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STEP_NAME=$(shell echo $(TCL_FILE) | cut -d '.' -f 1)
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STEP_NAME=$(shell echo $(TCL_FILE) | cut -d '.' -f 1)
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| Line 243... |
Line 219... |
# This is the common header, setting variables in the TCL file
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# This is the common header, setting variables in the TCL file
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tcl-common:
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tcl-common:
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$(Q)rm -f $(TCL_FILE);
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$(Q)rm -f $(TCL_FILE);
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$(Q)echo; echo "\tGenerating "$(TCL_FILE); echo
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$(Q)echo; echo "\tGenerating "$(TCL_FILE); echo
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$(Q)echo "set compile_directory "$(COMP_DIR) >> $(TCL_FILE)
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$(Q)echo "set compile_directory "$(COMP_DIR) >> $(TCL_FILE)
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$(Q)echo "set proj_name "$(PROJECT_NAME) >> $(TCL_FILE)
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$(Q)echo "set proj_name "$(DESIGN_NAME) >> $(TCL_FILE)
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$(Q)echo "set top_name "$(PROJECT_TOP_NAME) >> $(TCL_FILE)
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$(Q)echo "set top_name "$(DESIGN_TOP_NAME) >> $(TCL_FILE)
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$(Q)echo "set family "$(FPGA_FAMILY) >> $(TCL_FILE)
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$(Q)echo "set family "$(FPGA_FAMILY) >> $(TCL_FILE)
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$(Q)echo "set part "$(FPGA_PART) >> $(TCL_FILE)
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$(Q)echo "set part "$(FPGA_PART) >> $(TCL_FILE)
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$(Q)echo "set package "$(FPGA_PACKAGE) >> $(TCL_FILE)
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$(Q)echo "set package "$(FPGA_PACKAGE) >> $(TCL_FILE)
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$(Q)echo "set pdc_filename "$(PDC_FILE) >> $(TCL_FILE)
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$(Q)echo "set pdc_filename "$(PDC_FILE) >> $(TCL_FILE)
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$(Q)echo "set sdc_filename "$(SDC_FILE) >> $(TCL_FILE)
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$(Q)echo "set sdc_filename "$(SDC_FILE) >> $(TCL_FILE)
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| Line 339... |
Line 315... |
$(Q)echo " -max_paths 5 " \\ >> $(TCL_FILE)
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$(Q)echo " -max_paths 5 " \\ >> $(TCL_FILE)
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$(Q)echo " -max_expanded_paths 1 " \\ >> $(TCL_FILE)
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$(Q)echo " -max_expanded_paths 1 " \\ >> $(TCL_FILE)
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$(Q)echo " -include_user_sets no " \\ >> $(TCL_FILE)
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$(Q)echo " -include_user_sets no " \\ >> $(TCL_FILE)
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$(Q)echo " -include_pin_to_pin yes " \\ >> $(TCL_FILE)
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$(Q)echo " -include_pin_to_pin yes " \\ >> $(TCL_FILE)
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$(Q)echo " -select_clock_domains no " \\ >> $(TCL_FILE)
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$(Q)echo " -select_clock_domains no " \\ >> $(TCL_FILE)
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$(Q)echo " "$(PROJECT_NAME)"-timing.rpt " >> $(TCL_FILE)
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$(Q)echo " "$(DESIGN_NAME)"-timing.rpt " >> $(TCL_FILE)
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$(Q)echo " report " \\ >> $(TCL_FILE)
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$(Q)echo " report " \\ >> $(TCL_FILE)
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$(Q)echo " -type timing_violations " \\ >> $(TCL_FILE)
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$(Q)echo " -type timing_violations " \\ >> $(TCL_FILE)
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$(Q)echo " -analysis max " \\ >> $(TCL_FILE)
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$(Q)echo " -analysis max " \\ >> $(TCL_FILE)
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$(Q)echo " -use_slack_threshold no " \\ >> $(TCL_FILE)
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$(Q)echo " -use_slack_threshold no " \\ >> $(TCL_FILE)
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$(Q)echo " -limit_max_paths yes " \\ >> $(TCL_FILE)
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$(Q)echo " -limit_max_paths yes " \\ >> $(TCL_FILE)
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$(Q)echo " -max_paths 100 " \\ >> $(TCL_FILE)
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$(Q)echo " -max_paths 100 " \\ >> $(TCL_FILE)
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$(Q)echo " -max_expanded_paths 0 " \\ >> $(TCL_FILE)
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$(Q)echo " -max_expanded_paths 0 " \\ >> $(TCL_FILE)
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$(Q)echo " "$(PROJECT_NAME)"-timviol.rpt " >> $(TCL_FILE)
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$(Q)echo " "$(DESIGN_NAME)"-timviol.rpt " >> $(TCL_FILE)
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$(Q)echo " report " \\ >> $(TCL_FILE)
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$(Q)echo " report " \\ >> $(TCL_FILE)
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$(Q)echo " -type timing_violations " \\ >> $(TCL_FILE)
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$(Q)echo " -type timing_violations " \\ >> $(TCL_FILE)
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$(Q)echo " -analysis min " \\ >> $(TCL_FILE)
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$(Q)echo " -analysis min " \\ >> $(TCL_FILE)
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$(Q)echo " -use_slack_threshold no " \\ >> $(TCL_FILE)
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$(Q)echo " -use_slack_threshold no " \\ >> $(TCL_FILE)
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$(Q)echo " -limit_max_paths yes " \\ >> $(TCL_FILE)
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$(Q)echo " -limit_max_paths yes " \\ >> $(TCL_FILE)
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$(Q)echo " -max_paths 100 " \\ >> $(TCL_FILE)
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$(Q)echo " -max_paths 100 " \\ >> $(TCL_FILE)
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$(Q)echo " -max_expanded_paths 0 " \\ >> $(TCL_FILE)
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$(Q)echo " -max_expanded_paths 0 " \\ >> $(TCL_FILE)
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$(Q)echo " "$(PROJECT_NAME)"-timmindly.rpt " >> $(TCL_FILE)
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$(Q)echo " "$(DESIGN_NAME)"-timmindly.rpt " >> $(TCL_FILE)
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sdc-file:
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sdc-file:
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$(Q)for define in $(DESIGN_DEFINES); do export $$define=1; done; \
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$(Q)for define in $(DESIGN_DEFINES); do export $$define=1; done; \
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