URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [bench/] [verilog/] [orpsoc_testbench.v] - Diff between revs 408 and 411

Rev 408	Rev 411
Line 485...	Line 485...
`.Cas_n (sdram_cas_pad_o_to_sdram),`	`.Cas_n (sdram_cas_pad_o_to_sdram),`
`.We_n (sdram_we_pad_o_to_sdram),`	`.We_n (sdram_we_pad_o_to_sdram),`
`.Dqm (sdram_dqm_pad_o_to_sdram));`	`.Dqm (sdram_dqm_pad_o_to_sdram));`
`endif // `ifdef VERSATILE_SDRAM	`endif // `ifdef VERSATILE_SDRAM

	`ifdef VCD
`initial`	`reg vcd_go = 0;`
	`always @(vcd_go)`
`begin`	`begin`
`ifndef SIM_QUIET
`$display("\n* Starting simulation of design RTL.\n* Test: %s\n",`
`TEST_NAME_STRING );
`endif

`ifdef VCD
`ifdef VCD_DELAY	`ifdef VCD_DELAY
#(`VCD_DELAY);	#(`VCD_DELAY);
`endif	`endif

`// Delay by x insns`	`// Delay by x insns`
Line 520...	Line 516...
$dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});	$dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
`ifndef VCD_DEPTH	`ifndef VCD_DEPTH
`define VCD_DEPTH 0	`define VCD_DEPTH 0
`endif	`endif
$dumpvars(`VCD_DEPTH);	$dumpvars(`VCD_DEPTH);

	`end`
	`endif // `ifdef VCD

	`initial`
	`begin`
	`ifndef SIM_QUIET
	`$display("\n* Starting simulation of design RTL.\n* Test: %s\n",`
	`TEST_NAME_STRING );
	`endif

	`ifdef VCD
	`vcd_go = 1;`
`endif	`endif

`end // initial begin`	`end // initial begin`

`ifdef END_TIME	`ifdef END_TIME