OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [include/] [or1200_defines.v] - Diff between revs 530 and 854

Show entire file | Details | Blame | View Log

Rev 530	Rev 854
Line 697...	Line 697...
`define OR1200_OR32_JR 6'b010001	`define OR1200_OR32_JR 6'b010001
`define OR1200_OR32_JALR 6'b010010	`define OR1200_OR32_JALR 6'b010010
`define OR1200_OR32_MACI 6'b010011	`define OR1200_OR32_MACI 6'b010011
`/* */`	`/* */`
`define OR1200_OR32_LWZ 6'b100001	`define OR1200_OR32_LWZ 6'b100001
	`define OR1200_OR32_LWS 6'b100010
`define OR1200_OR32_LBZ 6'b100011	`define OR1200_OR32_LBZ 6'b100011
`define OR1200_OR32_LBS 6'b100100	`define OR1200_OR32_LBS 6'b100100
`define OR1200_OR32_LHZ 6'b100101	`define OR1200_OR32_LHZ 6'b100101
`define OR1200_OR32_LHS 6'b100110	`define OR1200_OR32_LHS 6'b100110
`define OR1200_OR32_ADDI 6'b100111	`define OR1200_OR32_ADDI 6'b100111

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.