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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [include/] [orpsoc-params.v] - Diff between revs 439 and 544

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Rev 439	Rev 544
Line 127...	Line 127...
`parameter wbs_d_eth0_data_width = 32;`	`parameter wbs_d_eth0_data_width = 32;`
`parameter wbs_d_eth0_addr_width = 12;`	`parameter wbs_d_eth0_addr_width = 12;`
`parameter wbm_eth0_data_width = 32;`	`parameter wbm_eth0_data_width = 32;`
`parameter wbm_eth0_addr_width = 32;`	`parameter wbm_eth0_addr_width = 32;`

	`// SDC controller defines`
	`parameter sdc_wb_adr = 8'h9e;`
	`parameter wbs_d_sdc_data_width = 32;`
	`parameter wbm_sdc_data_width = 32;`
	`parameter wbm_sdc_addr_width = 32;`

`// Memory sizing for wb_ram (simulation only)`	`// Memory sizing for wb_ram (simulation only)`
`parameter internal_sram_mem_span = 32'h0080_0000; // 8MB`	`parameter internal_sram_mem_span = 32'h0080_0000; // 8MB`
`parameter internal_sram_adr_width_for_span = 23; // log2(8192*1024)`	`parameter internal_sram_adr_width_for_span = 23; // log2(8192*1024)`

`//////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////`
Line 163...	Line 169...
`// Data bus //`	`// Data bus //`
`// //`	`// //`
`///////////////////////////`	`///////////////////////////`
`// Has auto foward to last slave when no address hits`	`// Has auto foward to last slave when no address hits`
`parameter dbus_arb_wb_addr_match_width = 8;`	`parameter dbus_arb_wb_addr_match_width = 8;`
`parameter dbus_arb_wb_num_slaves = 5;`	`parameter dbus_arb_wb_num_slaves = 4;`
`// Slave addresses`	`// Slave addresses`
`parameter dbus_arb_slave0_adr = 4'h0; // Main memory (SDRAM/FPGA SRAM)`	`parameter dbus_arb_slave0_adr = 4'h0; // Main memory (SDRAM/FPGA SRAM)`
`parameter dbus_arb_slave1_adr = eth0_wb_adr; // Ethernet 0`	`parameter dbus_arb_slave1_adr = eth0_wb_adr; // Ethernet 0`
	`parameter dbus_arb_slave2_adr = sdc_wb_adr;`

`///////////////////////////////`	`///////////////////////////////`
`// //`	`// //`
`// Byte-wide peripheral bus //`	`// Byte-wide peripheral bus //`
`// //`	`// //`

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [include/] [orpsoc-params.v] - Diff between revs 439 and 544