URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [versatile_mem_ctrl/] [versatile_mem_ctrl.v] - Diff between revs 408 and 411

Rev 408	Rev 411
Line 1070...	Line 1070...
`input [(ADDR_WIDTH-1):0] adr_b;`	`input [(ADDR_WIDTH-1):0] adr_b;`
`input we_a;`	`input we_a;`
`output [(DATA_WIDTH-1):0] q_b;`	`output [(DATA_WIDTH-1):0] q_b;`
`input clk_a, clk_b;`	`input clk_a, clk_b;`
`reg [(ADDR_WIDTH-1):0] adr_b_reg;`	`reg [(ADDR_WIDTH-1):0] adr_b_reg;`
`reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] ;`	`reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /synthesis syn_ramstyle = "no_rw_check"/;`
`always @ (posedge clk_a)`	`always @ (posedge clk_a)`
`if (we_a)`	`if (we_a)`
`ram[adr_a] <= d_a;`	`ram[adr_a] <= d_a;`
`always @ (posedge clk_b)`	`always @ (posedge clk_b)`
`adr_b_reg <= adr_b;`	`adr_b_reg <= adr_b;`