URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sim/] [bin/] [Makefile] - Diff between revs 449 and 468

Rev 449	Rev 468
Line 53...	Line 53...
`FPGA_VENDOR=actel`	`FPGA_VENDOR=actel`
`BOARD_NAME=ordb1a3pe1500`	`BOARD_NAME=ordb1a3pe1500`
`BOARD_DIR=$(PROJECT_ROOT)/boards/$(FPGA_VENDOR)/$(BOARD_NAME)`	`BOARD_DIR=$(PROJECT_ROOT)/boards/$(FPGA_VENDOR)/$(BOARD_NAME)`

`# Export BOARD_PATH for the software makefiles`	`# Export BOARD_PATH for the software makefiles`
`BOARD_PATH=$(BOARD_DIR)`	`BOARD=$(FPGA_VENDOR)/$(BOARD_NAME)`
`export BOARD_PATH`	`export BOARD`

`# Paths to other important parts of this test suite`	`# Paths to other important parts of this test suite`
`COMMON_RTL_DIR = $(PROJECT_ROOT)/rtl`	`COMMON_RTL_DIR = $(PROJECT_ROOT)/rtl`
`COMMON_RTL_VERILOG_DIR = $(COMMON_RTL_DIR)/verilog`	`COMMON_RTL_VERILOG_DIR = $(COMMON_RTL_DIR)/verilog`
`#COMMON_RTL_VHDL_DIR = $(COMMON_RTL_DIR)/vhdl`	`#COMMON_RTL_VHDL_DIR = $(COMMON_RTL_DIR)/vhdl`