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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
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Rev 468 |
Line 53... |
Line 53... |
FPGA_VENDOR=actel
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FPGA_VENDOR=actel
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BOARD_NAME=ordb1a3pe1500
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BOARD_NAME=ordb1a3pe1500
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BOARD_DIR=$(PROJECT_ROOT)/boards/$(FPGA_VENDOR)/$(BOARD_NAME)
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BOARD_DIR=$(PROJECT_ROOT)/boards/$(FPGA_VENDOR)/$(BOARD_NAME)
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# Export BOARD_PATH for the software makefiles
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# Export BOARD_PATH for the software makefiles
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BOARD_PATH=$(BOARD_DIR)
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BOARD=$(FPGA_VENDOR)/$(BOARD_NAME)
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export BOARD_PATH
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export BOARD
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# Paths to other important parts of this test suite
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# Paths to other important parts of this test suite
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COMMON_RTL_DIR = $(PROJECT_ROOT)/rtl
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COMMON_RTL_DIR = $(PROJECT_ROOT)/rtl
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COMMON_RTL_VERILOG_DIR = $(COMMON_RTL_DIR)/verilog
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COMMON_RTL_VERILOG_DIR = $(COMMON_RTL_DIR)/verilog
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#COMMON_RTL_VHDL_DIR = $(COMMON_RTL_DIR)/vhdl
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#COMMON_RTL_VHDL_DIR = $(COMMON_RTL_DIR)/vhdl
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