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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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PROJ_ROOT=../../../..
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PROJ_ROOT=../../../..
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# Figure out actual path the common software directory
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# Figure out actual path the common software directory
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SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw
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SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw
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# Set the BOARD_PATH to point to the root of this board build
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# Set the BOARD to be the path within the board/ path of the project that goes
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# to this project.
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BOARD=actel/ordb1a3pe1500
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BOARD=actel/ordb1a3pe1500
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# Set RTL_VERILOG_INCLUDE_DIR so software
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# Set RTL_VERILOG_INCLUDE_DIR so software
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RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include
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RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include
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