URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sw/] [Makefile.inc] - Diff between revs 480 and 483

Rev 480	Rev 483
Line 6...	Line 6...
`PROJ_ROOT=../../../..`	`PROJ_ROOT=../../../..`

`# Figure out actual path the common software directory`	`# Figure out actual path the common software directory`
`SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw`	`SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw`

`# Set the BOARD_PATH to point to the root of this board build`	`# Set the BOARD to be the path within the board/ path of the project that goes`
	`# to this project.`
`BOARD=actel/ordb1a3pe1500`	`BOARD=actel/ordb1a3pe1500`

`# Set RTL_VERILOG_INCLUDE_DIR so software`	`# Set RTL_VERILOG_INCLUDE_DIR so software`
`RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include`	`RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include`