URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sw/] [board/] [include/] [board.h] - Diff between revs 408 and 485

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Rev 408	Rev 485
Line 13...	Line 13...
`// ROM bootloader`	`// ROM bootloader`
`//`	`//`
`// Uncomment the appropriate bootloader define. This will effect the bootrom.S`	`// Uncomment the appropriate bootloader define. This will effect the bootrom.S`
`// file, which is compiled and converted into Verilog for inclusion at`	`// file, which is compiled and converted into Verilog for inclusion at`
`// synthesis time. See bootloader/bootloader.S for details on each option.`	`// synthesis time. See bootloader/bootloader.S for details on each option.`
	`#ifndef PRELOAD_RAM`
`#define BOOTROM_SPI_FLASH`	`#define BOOTROM_SPI_FLASH`
`//#define BOOTROM_GOTO_RESET`	`//#define BOOTROM_GOTO_RESET`
`//#define BOOTROM_LOOP_AT_ZERO`	`//#define BOOTROM_LOOP_AT_ZERO`
`//#define BOOTROM_LOOP_IN_ROM`	`//#define BOOTROM_LOOP_IN_ROM`
	`#else`
	`#define BOOTROM_GOTO_RESET`
	`#endif`

`//`	`//`
`// Defines for each core (memory map base, OR1200 interrupt line number, etc.)`	`// Defines for each core (memory map base, OR1200 interrupt line number, etc.)`
`//`	`//`
`#define SDRAM_BASE 0x0`	`#define SDRAM_BASE 0x0`
Line 89...	Line 92...
`//`	`//`
`// OR1200 tick timer period define`	`// OR1200 tick timer period define`
`//`	`//`
`#define TICKS_PER_SEC 100`	`#define TICKS_PER_SEC 100`

	`//`
	`// UART driver initialisation`
	`//`
	`#define UART_NUM_CORES 3`

	`#define UART_BASE_ADDRESSES_CSV \`
	`UART0_BASE, UART2_BASE, UART2_BASE`

	`#define UART_BAUD_RATES_CSV \`
	`UART0_BAUD_RATE, UART1_BAUD_RATE, UART1_BAUD_RATE`




`#endif`	`#endif`

`No newline at end of file`	`No newline at end of file`

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sw/] [board/] [include/] [board.h] - Diff between revs 408 and 485