URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [backend/] [par/] [bin/] [Makefile] - Diff between revs 638 and 866

Rev 638	Rev 866
Line 91...	Line 91...
`-timing -ol high -w $(XILINX_FLAGS) -o $@ -xe n $(NGD_FILE) $(PCF_FILE)`	`-timing -ol high -w $(XILINX_FLAGS) -o $@ -xe n $(NGD_FILE) $(PCF_FILE)`

`#This target uses Xilinx tools to Place & Route the design`	`#This target uses Xilinx tools to Place & Route the design`
`$(PARRED_NCD): $(MAPPED_NCD)`	`$(PARRED_NCD): $(MAPPED_NCD)`
`@echo; echo "\t#### PAR'ing ####";`	`@echo; echo "\t#### PAR'ing ####";`
`$(Q)par -w -ol high -xe n $(XILINX_FLAGS) $< $@ $(PCD_FILE)`	`$(Q)par -w -ol high -xe n $(XILINX_FLAGS) $< $@ $(PCF_FILE)`

`#This target uses Xilinx tools to generate a bitstream for download`	`#This target uses Xilinx tools to generate a bitstream for download`
`$(BIT_FILE): $(PARRED_NCD)`	`$(BIT_FILE): $(PARRED_NCD)`
`@echo; echo "\t#### Generating .bit file ####";`	`@echo; echo "\t#### Generating .bit file ####";`
`$(Q)bitgen -w $(XILINX_FLAGS) -g StartUpClk:JtagClk $< $@`	`$(Q)bitgen -w $(XILINX_FLAGS) -g StartUpClk:JtagClk $< $@`