URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [rtl/] [verilog/] [xilinx_ddr2/] [xilinx_ddr2_if.v] - Diff between revs 627 and 677

Rev 627	Rev 677
Line 241...	Line 241...
`wire ddr2_p0_rd_empty;`	`wire ddr2_p0_rd_empty;`
`wire [6:0] ddr2_p0_rd_count;`	`wire [6:0] ddr2_p0_rd_count;`
`wire ddr2_p0_rd_overflow;`	`wire ddr2_p0_rd_overflow;`
`wire ddr2_p0_rd_error;`	`wire ddr2_p0_rd_error;`
`wire ddr2_calib_done;`	`wire ddr2_calib_done;`
	`reg [1:0] ddr2_calib_done_r;`

`wire [30:0] readfrom_af_addr;`	`wire [30:0] readfrom_af_addr;`
`wire [30:0] writeback_af_addr;`	`wire [30:0] writeback_af_addr;`

wire [`DDR2_CACHE_NUM_LINES - 1 :0] cache_line_addr_validate;	wire [`DDR2_CACHE_NUM_LINES - 1 :0] cache_line_addr_validate;
Line 332...	Line 333...
`assign cached_addr_valid = \|(selected_cache_line & cache_line_addr_valid);`	`assign cached_addr_valid = \|(selected_cache_line & cache_line_addr_valid);`

`assign wb_req_addr_hit = (wb_req & cache_hit & cached_addr_valid);`	`assign wb_req_addr_hit = (wb_req & cache_hit & cached_addr_valid);`

`// Wishbone request detection`	`// Wishbone request detection`
`assign wb_req = wb_stb_i & wb_cyc_i & ddr2_calib_done & !sync;`	`assign wb_req = wb_stb_i & wb_cyc_i & ddr2_calib_done_r[0] & !sync;`

	`always @ (posedge wb_clk)`
	`ddr2_calib_done_r[1:0] <= {ddr2_calib_done, ddr2_calib_done_r[1]};`

`always @(posedge wb_clk)`	`always @(posedge wb_clk)`
`wb_req_r <= wb_req;`	`wb_req_r <= wb_req;`

`assign wb_req_new = wb_req & !wb_req_r;`	`assign wb_req_new = wb_req & !wb_req_r;`