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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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Rev 627 |
Rev 677 |
Line 241... |
Line 241... |
wire ddr2_p0_rd_empty;
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wire ddr2_p0_rd_empty;
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wire [6:0] ddr2_p0_rd_count;
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wire [6:0] ddr2_p0_rd_count;
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wire ddr2_p0_rd_overflow;
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wire ddr2_p0_rd_overflow;
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wire ddr2_p0_rd_error;
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wire ddr2_p0_rd_error;
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wire ddr2_calib_done;
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wire ddr2_calib_done;
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reg [1:0] ddr2_calib_done_r;
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wire [30:0] readfrom_af_addr;
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wire [30:0] readfrom_af_addr;
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wire [30:0] writeback_af_addr;
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wire [30:0] writeback_af_addr;
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wire [`DDR2_CACHE_NUM_LINES - 1 :0] cache_line_addr_validate;
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wire [`DDR2_CACHE_NUM_LINES - 1 :0] cache_line_addr_validate;
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Line 332... |
Line 333... |
assign cached_addr_valid = |(selected_cache_line & cache_line_addr_valid);
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assign cached_addr_valid = |(selected_cache_line & cache_line_addr_valid);
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assign wb_req_addr_hit = (wb_req & cache_hit & cached_addr_valid);
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assign wb_req_addr_hit = (wb_req & cache_hit & cached_addr_valid);
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// Wishbone request detection
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// Wishbone request detection
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assign wb_req = wb_stb_i & wb_cyc_i & ddr2_calib_done & !sync;
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assign wb_req = wb_stb_i & wb_cyc_i & ddr2_calib_done_r[0] & !sync;
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always @ (posedge wb_clk)
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ddr2_calib_done_r[1:0] <= {ddr2_calib_done, ddr2_calib_done_r[1]};
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always @(posedge wb_clk)
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always @(posedge wb_clk)
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wb_req_r <= wb_req;
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wb_req_r <= wb_req;
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assign wb_req_new = wb_req & !wb_req_r;
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assign wb_req_new = wb_req & !wb_req_r;
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