| Line 82... |
Line 82... |
XST_FILE=$(DESIGN_NAME).xst
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XST_FILE=$(DESIGN_NAME).xst
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PRJ_FILE=$(DESIGN_NAME).prj
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PRJ_FILE=$(DESIGN_NAME).prj
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NGC_FILE=$(DESIGN_NAME).ngc
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NGC_FILE=$(DESIGN_NAME).ngc
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NETLIST_FILE=$(DESIGN_NAME).v
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NETLIST_FILE=$(DESIGN_NAME).v
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COREGEN_DIR=$(BOARD_SYN_DIR)/coregen
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COREGEN_CGP_FILE=$(COREGEN_DIR)/coregen.cgp
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COREGEN_XCO_FILES=$(shell ls $(COREGEN_DIR)/*.xco)
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XST_PRJ_FILE_SRC_DECLARE=verilog work
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XST_PRJ_FILE_SRC_DECLARE=verilog work
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print-config:
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print-config:
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$(Q)echo; echo "\t### Synthesis make configuration ###"; echo
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$(Q)echo; echo "\t### Synthesis make configuration ###"; echo
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| Line 150... |
Line 153... |
$(Q)echo "NET rst_n_pad_i* TIG;" >> $@
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$(Q)echo "NET rst_n_pad_i* TIG;" >> $@
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$(Q)echo "# Define the two clock domains as timespecs" >> $@
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$(Q)echo "# Define the two clock domains as timespecs" >> $@
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$(Q)echo "#NET dcm0_clkdv TNM_NET=\"wb_clk\";" >> $@
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$(Q)echo "#NET dcm0_clkdv TNM_NET=\"wb_clk\";" >> $@
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$(Q)echo "#TIMESPEC \"TS_wb_clk\" = PERIOD \"wb_clk\" 20 ns HIGH 10;" >> $@
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$(Q)echo "#TIMESPEC \"TS_wb_clk\" = PERIOD \"wb_clk\" 20 ns HIGH 10;" >> $@
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# Generate coregen cores
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coregen:
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$(Q)echo; echo "#### Running CORE Gen ####"; echo
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$(Q)(. $(XILINX_SETTINGS_SCRIPT))
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$(Q)$(shell cp $(COREGEN_XCO_FILES) .)
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$(Q)$(shell cp $(COREGEN_CGP_FILE) .)
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$(Q)for file in $(COREGEN_XCO_FILES); do \
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coregen -b $(notdir $$file) -p $(notdir $(COREGEN_CGP_FILE)) $(XILINX_FLAGS); \
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done
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# XST command
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# XST command
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$(NGC_FILE): $(PRJ_FILE) $(XST_FILE) $(XCF_FILE) $(GENERATED_DEFINES)
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$(NGC_FILE): $(PRJ_FILE) $(XST_FILE) $(XCF_FILE) $(GENERATED_DEFINES) coregen
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$(Q)echo; echo "\t#### Running XST ####"; echo;
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$(Q)echo; echo "\t#### Running XST ####"; echo;
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$(Q)(. $(XILINX_SETTINGS_SCRIPT) ; xst -ifn $(XST_FILE) $(XILINX_FLAGS) $(XST_FLAGS) )
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$(Q)(. $(XILINX_SETTINGS_SCRIPT) ; xst -ifn $(XST_FILE) $(XILINX_FLAGS) $(XST_FLAGS) )
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$(Q)echo
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$(Q)echo
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netlist: $(NETLIST_FILE)
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netlist: $(NETLIST_FILE)
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| Line 166... |
Line 179... |
$(Q)(. $(XILINX_SETTINGS_SCRIPT) ; \
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$(Q)(. $(XILINX_SETTINGS_SCRIPT) ; \
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netgen -sim -aka -dir . -ofmt verilog $< -w $@ )
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netgen -sim -aka -dir . -ofmt verilog $< -w $@ )
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clean:
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clean:
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$(Q)rm -rf *.* xst
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$(Q)rm -rf *.* xst tmp _xmsgs xlnx_auto* *.lso
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clean-sw:
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clean-sw:
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$(MAKE) -C $(PROJECT_ROOT)/sw/lib distclean
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$(MAKE) -C $(PROJECT_ROOT)/sw/lib distclean
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distclean: clean-sw clean
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distclean: clean-sw clean
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