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######################################################################
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#### ####
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#### ORPSoC Xilinx backend Makefile ####
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#### ####
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#### Author(s): ####
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#### - Julius Baxter, julius@opencores.org ####
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#### ####
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#### ####
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######################################################################
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#### ####
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#### Copyright (C) 2009,2010 Authors and OPENCORES.ORG ####
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#### ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### removed from the file and that any derivative work contains ####
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#### the original copyright notice and the associated disclaimer. ####
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#### ####
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#### This source file is free software; you can redistribute it ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### Public License as published by the Free Software Foundation; ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### later version. ####
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#### ####
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#### This source is distributed in the hope that it will be ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### details. ####
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#### ####
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#### You should have received a copy of the GNU Lesser General ####
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#### Public License along with this source; if not, download it ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### ####
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######################################################################
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# Name of the directory we're currently in
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CUR_DIR=$(shell pwd)
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# The root path of the board build
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BOARD_DIR ?=$(CUR_DIR)/../../..
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PROJECT_ROOT=$(BOARD_DIR)/../../..
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SYN_DIR=$(BOARD_DIR)/syn/xst
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SYN_RUN_DIR=$(SYN_DIR)/run
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BOARD_BACKEND_DIR=$(BOARD_DIR)/backend/bin
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DESIGN_NAME=orpsoc
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BOARD_NAME=ml501
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# Set V=1 when calling make to enable verbose output
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# mainly for debugging purposes.
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ifeq ($(V), 1)
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Q=
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else
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Q ?=@
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endif
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BOARD_RTL_DIR=$(BOARD_DIR)/rtl
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BOARD_RTL_VERILOG_DIR=$(BOARD_RTL_DIR)/verilog
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# Only 1 include path for board builds - their own!
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BOARD_RTL_VERILOG_INCLUDE_DIR=$(BOARD_RTL_VERILOG_DIR)/include
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BOARD_DESIGN_VERILOG_DEFINES=$(BOARD_RTL_VERILOG_INCLUDE_DIR)/$(DESIGN_NAME)-defines.v
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DEFINES_FILE_CUTOFF=$(shell grep -n "end of included module defines" $(BOARD_DESIGN_VERILOG_DEFINES) | cut -d ':' -f 1)
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DESIGN_DEFINES=$(shell cat $(BOARD_DESIGN_VERILOG_DEFINES) | sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g )
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# Rule to look at what defines are being extracted from main file
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print-defines:
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@echo; echo "\t### Design defines ###"; echo
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@echo "\tParsing "$(BOARD_DESIGN_VERILOG_DEFINES)" and exporting:"
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@echo $(DESIGN_DEFINES)
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# Backend tool path
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# Check that the XILINX_PATH variable is set
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ifeq ($(XILINX_PATH),)
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$(error XILINX_PATH environment variable not set. Set it and rerun)
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endif
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XILINX_SETTINGS_SCRIPT=$(XILINX_PATH)/settings32.sh
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XILINX_SETTINGS_SCRIPT_EXISTS=$(shell if [ -e $(XILINX_SETTINGS_SCRIPT) ]; then echo 1; else echo 0; fi)
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ifeq ($(XILINX_SETTINGS_SCRIPT_EXISTS),0)
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$(error XILINX_PATH variable not set correctly. Cannot find $$XILINX_PATH/settings32.sh)
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endif
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#
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# Options for Xilinx PAR tools
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#
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FPGA_PART=xc5vlx50-ff676-1
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XILINX_FLAGS=-intstyle silent
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XILINX_MAP_FLAGS=-logic_opt off
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XILINX_AREA_TARGET = speed
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TIMING_REPORT_OPTIONS = -u 1000 -e 1000
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SPI_FLASH_SIZE_KBYTES ?=2048
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SPI_BOOTLOADER_SW_OFFSET_HEX ?=1c0000
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print-config:
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$(Q)echo; echo "\t### Backend make configuration ###"; echo
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$(Q)echo "\tFPGA_PART="$(FPGA_PART)
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$(Q)echo "\tXILINX_FLAGS="$(XILINX_FLAGS)
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$(Q)echo "\tXILINX_MAP_FLAGS="$(XILINX_MAP_FLAGS)
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$(Q)echo "\tXILINX_AREA_TARGET="$(XILINX_AREA_TARGET)
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$(Q)echo "\tTIMING_REPORT_OPTIONS="$(TIMING_REPORT_OPTIONS)
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$(Q)echo "\tSPI_FLASH_SIZE_KBYTES="$(SPI_FLASH_SIZE_KBYTES)
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$(Q)echo "\tSPI_BOOTLOADER_SW_OFFSET_HEX="$(SPI_BOOTLOADER_SW_OFFSET_HEX)
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NGC_FILE=$(SYN_RUN_DIR)/$(DESIGN_NAME).ngc
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NGD_FILE=$(DESIGN_NAME).ngd
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UCF_FILE=../bin/$(BOARD_NAME).ucf
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MAPPED_NCD=$(DESIGN_NAME)_mapped.ncd
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PARRED_NCD=$(DESIGN_NAME).ncd
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PCF_FILE=$(DESIGN_NAME).pcf
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BIT_FILE=$(DESIGN_NAME).bit
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BIT_FILE_FOR_SPI=$(DESIGN_NAME)_spiboot.bit
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BATCH_FILE=$(DESIGN_NAME).batch
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MCS_FILE=$(DESIGN_NAME).mcs
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$(NGC_FILE):
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$(Q)$(MAKE) -C $(SYN_RUN_DIR) $(DESIGN_NAME).ngc
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$(NGD_FILE): $(UCF_FILE) $(NGC_FILE)
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@echo; echo "\t#### Running NGDBuild ####";
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$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
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ngdbuild -p $(FPGA_PART) -sd $(BOARD_BACKEND_DIR) -uc $(UCF_FILE) \
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$(NGC_FILE) $@ )
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#This target uses Xilinx tools to perform Mapping
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$(MAPPED_NCD): $(NGD_FILE)
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@echo; echo "\t#### Mapping ####";
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$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
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export XIL_MAP_NO_DSP_AUTOREG=1 && \
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export XIL_MAP_ALLOW_ANY_DLL_INPUT=1 && \
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map -p $(FPGA_PART) -detail -pr b -cm ${XILINX_AREA_TARGET} \
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-timing -ol high -w $(XILINX_FLAGS) -o $@ -xe n $(NGD_FILE) $(PCF_FILE))
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#This target uses Xilinx tools to Place & Route the design
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$(PARRED_NCD): $(MAPPED_NCD)
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@echo; echo "\t#### PAR'ing ####";
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$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
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par -w -pl high -rl high $(XILINX_FLAGS) $< $@ $(PCD_FILE) )
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#This target uses Xilinx tools to generate a bitstream for download
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$(BIT_FILE): $(PARRED_NCD)
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@echo; echo "\t#### Generating .bit file ####";
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$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
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bitgen -w $(XILINX_FLAGS) -g StartUpClk:JtagClk $< $@ )
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$(BIT_FILE_FOR_SPI): $(PARRED_NCD)
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@echo; echo "\t#### Generating .bit file for SPI load ####";
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$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
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bitgen -w $(XILINX_FLAGS) -g StartUpClk:CClk $< $@ )
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ifeq ($(BOOTLOADER_BIN),)
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$(MCS_FILE): $(BIT_FILE_FOR_SPI)
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@echo; echo "\t#### Generating .mcs file for SPI load ####";
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$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
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promgen -spi -p mcs -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< )
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else
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$(MCS_FILE): $(BIT_FILE_FOR_SPI)
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@echo; echo "\t#### Generating .mcs file for SPI load ####";
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$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
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promgen -spi -p mcs -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< \
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-data_file up $(SPI_BOOTLOADER_SW_OFFSET_HEX) $(BOOTLOADER_BIN) \
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)
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endif
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#this target downloads the bitstream to the target fpga
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download: $(BIT_FILE) $(BATCH_FILE)
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$(Q)( . ${XILINX_PATH}/settings32.sh && \
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impact -batch $(BATCH_FILE) )
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#This target uses netgen to make a simulation netlist
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netlist: $(PARRED_NCD)
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@echo; echo "\t#### Generating netlist ####";
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$(Q)(. $(XILINX_SETTINGS_SCRIPT) && \
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netgen -ofmt verilog -sim -dir netlist -pcf $(PCF_FILE) $<)
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#This one uses TRCE to make a timing report
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timingreport: $(PARRED_NCD)
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@echo; echo "\t#### Generating timing report ####";
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$(Q)(. $(XILINX_SETTINGS_SCRIPT) && \
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trce $(TIMING_REPORT_OPTIONS) $< )
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clean:
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$(Q)rm -rf *.*
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clean-syn:
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$(Q)$(MAKE) -C $(SYN_RUN_DIR) clean-all
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clean-all: clean-syn clean
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.PRECIOUS : $(PARRED_NCD) $(MAPPED_NCD) $(NGC_FILE) $(NGD_FILE) $(BIT_FILE) $(BIT_FILE_FOR_SPI)
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