| Line 6... |
Line 6... |
#### - Julius Baxter, julius@opencores.org ####
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#### - Julius Baxter, julius@opencores.org ####
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#### ####
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#### ####
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#### ####
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#### ####
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######################################################################
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######################################################################
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#### ####
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#### ####
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#### Copyright (C) 2009,2010 Authors and OPENCORES.ORG ####
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#### Copyright (C) 2009,2010,2011 Authors and OPENCORES.ORG ####
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#### ####
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#### ####
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#### This source file may be used and distributed without ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### restriction provided that this copyright statement is not ####
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#### removed from the file and that any derivative work contains ####
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#### removed from the file and that any derivative work contains ####
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#### the original copyright notice and the associated disclaimer. ####
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#### the original copyright notice and the associated disclaimer. ####
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| Line 35... |
Line 35... |
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# Name of the directory we're currently in
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# Name of the directory we're currently in
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CUR_DIR=$(shell pwd)
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CUR_DIR=$(shell pwd)
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|
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# The root path of the board build
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# The root path of the board build
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BOARD_DIR ?=$(CUR_DIR)/../../..
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BOARD_ROOT ?=$(CUR_DIR)/../../..
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PROJECT_ROOT=$(BOARD_DIR)/../../..
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include $(BOARD_ROOT)/Makefile.inc
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|
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SYN_DIR=$(BOARD_DIR)/syn/xst
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SYN_RUN_DIR=$(SYN_DIR)/run
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BOARD_BACKEND_DIR=$(BOARD_DIR)/backend/bin
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DESIGN_NAME=orpsoc
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BOARD_NAME=ml501
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|
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# Set V=1 when calling make to enable verbose output
|
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# mainly for debugging purposes.
|
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ifeq ($(V), 1)
|
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Q=
|
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else
|
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Q ?=@
|
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endif
|
|
|
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BOARD_RTL_DIR=$(BOARD_DIR)/rtl
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BOARD_RTL_VERILOG_DIR=$(BOARD_RTL_DIR)/verilog
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# Only 1 include path for board builds - their own!
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BOARD_RTL_VERILOG_INCLUDE_DIR=$(BOARD_RTL_VERILOG_DIR)/include
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BOARD_DESIGN_VERILOG_DEFINES=$(BOARD_RTL_VERILOG_INCLUDE_DIR)/$(DESIGN_NAME)-defines.v
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|
|
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DEFINES_FILE_CUTOFF=$(shell grep -n "end of included module defines" $(BOARD_DESIGN_VERILOG_DEFINES) | cut -d ':' -f 1)
|
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DESIGN_DEFINES=$(shell cat $(BOARD_DESIGN_VERILOG_DEFINES) | sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g )
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|
|
# Rule to look at what defines are being extracted from main file
|
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print-defines:
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@echo; echo "\t### Design defines ###"; echo
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@echo "\tParsing "$(BOARD_DESIGN_VERILOG_DEFINES)" and exporting:"
|
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@echo $(DESIGN_DEFINES)
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|
|
|
|
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# Backend tool path
|
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# Check that the XILINX_PATH variable is set
|
|
ifeq ($(XILINX_PATH),)
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$(error XILINX_PATH environment variable not set. Set it and rerun)
|
|
endif
|
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XILINX_SETTINGS_SCRIPT=$(XILINX_PATH)/settings32.sh
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XILINX_SETTINGS_SCRIPT_EXISTS=$(shell if [ -e $(XILINX_SETTINGS_SCRIPT) ]; then echo 1; else echo 0; fi)
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ifeq ($(XILINX_SETTINGS_SCRIPT_EXISTS),0)
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$(error XILINX_PATH variable not set correctly. Cannot find $$XILINX_PATH/settings32.sh)
|
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endif
|
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|
|
|
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#
|
#
|
# Options for Xilinx PAR tools
|
# Options for Xilinx PAR tools
|
#
|
#
|
FPGA_PART=xc5vlx50-ff676-1
|
FPGA_PART=xc5vlx50-ff676-1
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| Line 103... |
Line 59... |
$(Q)echo "\tXILINX_AREA_TARGET="$(XILINX_AREA_TARGET)
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$(Q)echo "\tXILINX_AREA_TARGET="$(XILINX_AREA_TARGET)
|
$(Q)echo "\tTIMING_REPORT_OPTIONS="$(TIMING_REPORT_OPTIONS)
|
$(Q)echo "\tTIMING_REPORT_OPTIONS="$(TIMING_REPORT_OPTIONS)
|
$(Q)echo "\tSPI_FLASH_SIZE_KBYTES="$(SPI_FLASH_SIZE_KBYTES)
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$(Q)echo "\tSPI_FLASH_SIZE_KBYTES="$(SPI_FLASH_SIZE_KBYTES)
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$(Q)echo "\tSPI_BOOTLOADER_SW_OFFSET_HEX="$(SPI_BOOTLOADER_SW_OFFSET_HEX)
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$(Q)echo "\tSPI_BOOTLOADER_SW_OFFSET_HEX="$(SPI_BOOTLOADER_SW_OFFSET_HEX)
|
|
|
|
NGC_FILE=$(BOARD_SYN_RUN_DIR)/$(DESIGN_NAME).ngc
|
|
|
NGC_FILE=$(SYN_RUN_DIR)/$(DESIGN_NAME).ngc
|
|
NGD_FILE=$(DESIGN_NAME).ngd
|
NGD_FILE=$(DESIGN_NAME).ngd
|
UCF_FILE=../bin/$(BOARD_NAME).ucf
|
UCF_FILE=../bin/$(BOARD_NAME).ucf
|
MAPPED_NCD=$(DESIGN_NAME)_mapped.ncd
|
MAPPED_NCD=$(DESIGN_NAME)_mapped.ncd
|
PARRED_NCD=$(DESIGN_NAME).ncd
|
PARRED_NCD=$(DESIGN_NAME).ncd
|
PCF_FILE=$(DESIGN_NAME).pcf
|
PCF_FILE=$(DESIGN_NAME).pcf
|
| Line 117... |
Line 71... |
BIT_FILE_FOR_SPI=$(DESIGN_NAME)_spiboot.bit
|
BIT_FILE_FOR_SPI=$(DESIGN_NAME)_spiboot.bit
|
BATCH_FILE=$(DESIGN_NAME).batch
|
BATCH_FILE=$(DESIGN_NAME).batch
|
MCS_FILE=$(DESIGN_NAME).mcs
|
MCS_FILE=$(DESIGN_NAME).mcs
|
|
|
$(NGC_FILE):
|
$(NGC_FILE):
|
$(Q)$(MAKE) -C $(SYN_RUN_DIR) $(DESIGN_NAME).ngc
|
$(Q)$(MAKE) -C $(BOARD_SYN_RUN_DIR) $(DESIGN_NAME).ngc
|
|
|
$(NGD_FILE): $(UCF_FILE) $(NGC_FILE)
|
$(NGD_FILE): $(UCF_FILE) $(NGC_FILE)
|
@echo; echo "\t#### Running NGDBuild ####";
|
@echo; echo "\t#### Running NGDBuild ####";
|
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
|
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
|
ngdbuild -p $(FPGA_PART) -sd $(BOARD_BACKEND_DIR) -uc $(UCF_FILE) \
|
ngdbuild -p $(FPGA_PART) -sd $(BOARD_BACKEND_BIN_DIR) -uc $(UCF_FILE) \
|
$(NGC_FILE) $@ )
|
$(NGC_FILE) $@ )
|
|
|
#This target uses Xilinx tools to perform Mapping
|
#This target uses Xilinx tools to perform Mapping
|
$(MAPPED_NCD): $(NGD_FILE)
|
$(MAPPED_NCD): $(NGD_FILE)
|
@echo; echo "\t#### Mapping ####";
|
@echo; echo "\t#### Mapping ####";
|
| Line 188... |
Line 142... |
|
|
clean:
|
clean:
|
$(Q)rm -rf *.* xlnx_auto*
|
$(Q)rm -rf *.* xlnx_auto*
|
|
|
clean-syn:
|
clean-syn:
|
$(Q)$(MAKE) -C $(SYN_RUN_DIR) distclean
|
$(Q)$(MAKE) -C $(BOARD_SYN_RUN_DIR) distclean
|
|
|
distclean: clean-syn clean
|
distclean: clean-syn clean
|
|
|
.PRECIOUS : $(PARRED_NCD) $(MAPPED_NCD) $(NGC_FILE) $(NGD_FILE) $(BIT_FILE) $(BIT_FILE_FOR_SPI)
|
.PRECIOUS : $(PARRED_NCD) $(MAPPED_NCD) $(NGC_FILE) $(NGD_FILE) $(BIT_FILE) $(BIT_FILE_FOR_SPI)
|
