URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [include/] [ddr2_model_preload.v] - Diff between revs 412 and 415

Rev 412	Rev 415
Line 51...	Line 51...

`//$display("Writing 0x%h, ramline=%d",ddr2_ram_mem_line, ram_ptr);`	`//$display("Writing 0x%h, ramline=%d",ddr2_ram_mem_line, ram_ptr);`

`end // for (ram_ptr = 0 ; ram_ptr < ...`	`end // for (ram_ptr = 0 ; ram_ptr < ...`
`$display("(%t) * DDR2 RAM %1d preloaded",$time, i);`	`$display("(%t) * DDR2 RAM %1d preloaded",$time, i);`
`end // initial begin`

`No newline at end of file`	`No newline at end of file`