| Line 70... |
Line 70... |
reg [7:0] st_data;
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reg [7:0] st_data;
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reg [31:0] lfsr;
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reg [31:0] lfsr;
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integer lfsr_last_byte;
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integer lfsr_last_byte;
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// Is number of ethernet packets to send if doing the eth-rx test.
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// Is number of ethernet packets to send if doing the eth-rx test.
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parameter eth_stim_num_rx_only_num_packets = 500; // Set to 0 for continuous RX
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parameter eth_stim_num_rx_only_num_packets = 12; // Set to 0 for continuous RX
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parameter eth_stim_num_rx_only_packet_size = 512;
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parameter eth_stim_num_rx_only_packet_size = 60;
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parameter eth_stim_num_rx_only_packet_size_change = 2'b01; // 2'b01: Increment
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parameter eth_stim_num_rx_only_packet_size_change = 2'b01; // 2'b01: Increment
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parameter eth_stim_num_rx_only_packet_size_change_amount = 1;
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parameter eth_stim_num_rx_only_packet_size_change_amount = 127;
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parameter eth_stim_num_rx_only_IPG = 800000000; // ns
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parameter eth_stim_num_rx_only_IPG = 180_000_000; // ps
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// Do call/response test
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// Do call/response test
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reg eth_stim_do_rx_reponse_to_tx;
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reg eth_stim_do_rx_reponse_to_tx;
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| Line 93... |
Line 93... |
//parameter rx_while_tx_min_packet_size = max_eth_packet_size;
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//parameter rx_while_tx_min_packet_size = max_eth_packet_size;
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parameter rx_while_tx_min_packet_size = 32;
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parameter rx_while_tx_min_packet_size = 32;
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// Use the smallest possible IPG
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// Use the smallest possible IPG
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parameter eth_stim_use_min_IPG = 0;
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parameter eth_stim_use_min_IPG = 0;
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parameter eth_stim_IPG_delay_max = 500_000; // Maximum 500uS ga
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parameter eth_stim_IPG_delay_max = 500_000_000; // Maximum 500uS ga
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//parameter eth_stim_IPG_delay_max = 100_000_000; // Maximum 100mS between packets
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//parameter eth_stim_IPG_delay_max = 100_000_000; // Maximum 100mS between packets
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parameter eth_stim_IPG_min_10mb = 9600; // 9.6 uS
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parameter eth_stim_IPG_min_10mb = 9600_000; // 9.6 uS
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parameter eth_stim_IPG_min_100mb = 800; // 860+~100 = 960 nS 100MBit min IPG
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parameter eth_stim_IPG_min_100mb = 800_000; // 860+~100 = 960 nS 100MBit min IPG
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parameter eth_stim_check_rx_packet_contents = 1;
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parameter eth_stim_check_rx_packet_contents = 1;
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parameter eth_stim_check_tx_packet_contents = 1;
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parameter eth_stim_check_tx_packet_contents = 1;
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|
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parameter eth_inject_errors = 0;
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parameter eth_inject_errors = 0;
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| Line 113... |
Line 113... |
// For 25MHz sdram controller, use following:
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// For 25MHz sdram controller, use following:
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//parameter Td_rx_packet_check = (`BOARD_CLOCK_PERIOD * 2000);
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//parameter Td_rx_packet_check = (`BOARD_CLOCK_PERIOD * 2000);
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// For 64MHz sdram controller, use following:
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// For 64MHz sdram controller, use following:
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parameter Td_rx_packet_check = (`BOARD_CLOCK_PERIOD * 500);
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parameter Td_rx_packet_check = (`BOARD_CLOCK_PERIOD * 500);
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|
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integer expected_rxbd;// init to 0
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integer expected_rxbd;// init to 0
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integer expected_txbd;
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integer expected_txbd;
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|
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wire ethmac_rxen;
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wire ethmac_rxen;
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wire ethmac_txen;
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wire ethmac_txen;
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| Line 579... |
Line 577... |
end
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end
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endtask // get_byte_from_xilinx_ddr2
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endtask // get_byte_from_xilinx_ddr2
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|
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`endif
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`endif
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|
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`ifdef XILINX_DDR2
|
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task sync_controller_cache_xilinx_ddr;
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begin
|
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// Sync cache (writeback dirty lines) with external memory
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dut.xilinx_ddr2_0.xilinx_ddr2_if0.do_sync;
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// Wait for it to occur.
|
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while (dut.xilinx_ddr2_0.xilinx_ddr2_if0.sync)
|
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#100;
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|
|
|
// Wait just incase writeback of all data hasn't fully occurred.
|
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// 4uS, in case RAM needs to refresh while writing back.
|
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#4_000_000;
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|
|
|
|
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end
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endtask // sync_controller_cache_xilinx_ddr
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`endif
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|
|
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//
|
//
|
// Check packet TX'd by MAC was good
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// Check packet TX'd by MAC was good
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//
|
//
|
task check_tx_packet;
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task check_tx_packet;
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| Line 615... |
Line 631... |
eth_phy0.tx_len-4, tx_len_bd);
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eth_phy0.tx_len-4, tx_len_bd);
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#100;
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#100;
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$finish;
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$finish;
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end
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end
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|
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`ifdef XILINX_DDR2
|
|
sync_controller_cache_xilinx_ddr;
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`endif
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|
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get_bd_addr(tx_bd_num, tx_bd_addr);
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get_bd_addr(tx_bd_num, tx_bd_addr);
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|
|
// We're never going to be using more than about 256K of receive buffer
|
// We're never going to be using more than about 256K of receive buffer
|
// so let's lop off the top bit of the address pointer - we only want
|
// so let's lop off the top bit of the address pointer - we only want
|
// the offset from the base of the memory bank
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// the offset from the base of the memory bank
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| Line 632... |
Line 652... |
begin
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begin
|
//$display("Checking address in tx bd 0x%0h",txpnt_sdram);
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//$display("Checking address in tx bd 0x%0h",txpnt_sdram);
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sdram_byte = 8'hx;
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sdram_byte = 8'hx;
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`ifdef RAM_WB
|
`ifdef RAM_WB
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sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(txpnt_sdram);
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sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(txpnt_sdram);
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`endif
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`else
|
`ifdef VERSATILE_SDRAM
|
`ifdef VERSATILE_SDRAM
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sdram0.get_byte(txpnt_sdram,sdram_byte);
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sdram0.get_byte(txpnt_sdram,sdram_byte);
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`endif
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`else
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`ifdef XILINX_DDR2
|
`ifdef XILINX_DDR2
|
get_byte_from_xilinx_ddr2(txpnt_sdram, sdram_byte);
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get_byte_from_xilinx_ddr2(txpnt_sdram, sdram_byte);
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`endif
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`else
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if (sdram_byte === 8'hx)
|
|
begin
|
|
$display(" * Error: sdram_byte was %x", sdram_byte);
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$display(" * Error: sdram_byte was %x", sdram_byte);
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|
|
$display(" * eth_stim needs to be able to access the main memory to check packet rx/tx");
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$display(" * eth_stim needs to be able to access the main memory to check packet rx/tx");
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$display(" * RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h",
|
|
tx_bd_addr, txpnt_wb);
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|
$finish;
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$finish;
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end
|
|
|
|
|
`endif
|
|
`endif
|
|
`endif
|
|
|
phy_byte = eth_phy0.tx_mem[buffer];
|
phy_byte = eth_phy0.tx_mem[buffer];
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// Debugging output
|
// Debugging output
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//$display("txpnt_sdram = 0x%h, sdram_byte = 0x%h, buffer = 0x%h, phy_byte = 0x%h", txpnt_sdram, sdram_byte, buffer, phy_byte);
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//$display("txpnt_sdram = 0x%h, sdram_byte = 0x%h, buffer = 0x%h, phy_byte = 0x%h", txpnt_sdram, sdram_byte, buffer, phy_byte);
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|
|
if (phy_byte !== sdram_byte)
|
if (phy_byte !== sdram_byte)
|
begin
|
begin
|
`TIME;
|
`TIME;
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$display("*E Wrong byte (%d) of TX packet! ram = %h, phy = %h",buffer, sdram_byte, phy_byte);
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$display("*E Wrong byte (%d) of TX packet! ram = %h, phy = %h",buffer, sdram_byte, phy_byte);
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failure = 1;
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failure = 1;
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| Line 1105... |
Line 1124... |
|
|
reg [31:0] rxpnt_wb; // Pointer in array to where data should be
|
reg [31:0] rxpnt_wb; // Pointer in array to where data should be
|
reg [24:0] rxpnt_sdram; // byte address from CPU in RAM
|
reg [24:0] rxpnt_sdram; // byte address from CPU in RAM
|
reg [15:0] sdram_short;
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reg [15:0] sdram_short;
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reg [7:0] sdram_byte;
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reg [7:0] sdram_byte;
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//reg [7:0] phy_rx_mem [0:2000];
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|
|
|
integer i;
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integer i;
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integer failure;
|
integer failure;
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|
|
begin
|
begin
|
| Line 1130... |
Line 1148... |
|
|
// Delay some time - takes a bit for the Wishbone FSM to pipe out the
|
// Delay some time - takes a bit for the Wishbone FSM to pipe out the
|
// packet over Wishbone and into whatever memory it's going into
|
// packet over Wishbone and into whatever memory it's going into
|
#Td_rx_packet_check;
|
#Td_rx_packet_check;
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|
|
|
`ifdef XILINX_DDR2
|
|
sync_controller_cache_xilinx_ddr;
|
|
`endif
|
|
|
// Ok, buffer filled, let's get its offset in memory
|
// Ok, buffer filled, let's get its offset in memory
|
get_bd_addr(rx_bd_num, rx_bd_addr);
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get_bd_addr(rx_bd_num, rx_bd_addr);
|
|
|
$display("(%t) Check RX packet: bd %d: 0x%h, addr 0x%h",$time,
|
$display("(%t) Check RX packet: bd %d: 0x%h, addr 0x%h",$time,
|
rx_bd_num, rx_bd_lenstat, rx_bd_addr);
|
rx_bd_num, rx_bd_lenstat, rx_bd_addr);
|
| Line 1152... |
Line 1174... |
|
|
for (i=0;i<len;i=i+1)
|
for (i=0;i<len;i=i+1)
|
begin
|
begin
|
|
|
sdram_byte = 8'hx;
|
sdram_byte = 8'hx;
|
`ifdef RAM_WB
|
|
sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(rxpnt_sdram);
|
|
`endif
|
|
`ifdef VERSATILE_SDRAM
|
|
sdram0.get_byte(rxpnt_sdram,sdram_byte);
|
|
`endif
|
|
`ifdef XILINX_DDR2
|
`ifdef XILINX_DDR2
|
get_byte_from_xilinx_ddr2(rxpnt_sdram, sdram_byte);
|
get_byte_from_xilinx_ddr2(rxpnt_sdram, sdram_byte);
|
`endif
|
`else
|
if (sdram_byte === 8'hx)
|
|
begin
|
|
$display(" * Error:");
|
$display(" * Error:");
|
|
|
$display(" * eth_stim needs to be able to access the main memory to check packet rx/tx");
|
$display(" * eth_stim needs to be able to access the main memory to check packet rx/tx");
|
$display("RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h",
|
|
rx_bd_addr, rxpnt_wb);
|
|
$finish;
|
$finish;
|
end
|
`endif
|
|
|
phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr];//phy_rx_mem[buffer]; //eth_phy0.rx_mem[buffer];
|
phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr];
|
|
|
if (phy_byte !== sdram_byte)
|
if (phy_byte !== sdram_byte)
|
begin
|
begin
|
// `TIME;
|
// `TIME;
|
$display("*E Wrong byte (%5d) of RX packet %5d! phy = %h, ram = %h",
|
$display("*E Wrong byte (%5d) of RX packet %5d. phy mem = %h, ram = %h",
|
i, eth_rx_num_packets_checked, phy_byte, sdram_byte);
|
i, eth_rx_num_packets_checked, phy_byte, sdram_byte);
|
failure = 1;
|
failure = 1;
|
end
|
end
|
|
|
eth_rx_sent_circbuf_read_ptr = (eth_rx_sent_circbuf_read_ptr+1)&
|
eth_rx_sent_circbuf_read_ptr = (eth_rx_sent_circbuf_read_ptr+1)&
|
