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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [orpsoc_testbench.v] - Diff between revs 415 and 655

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Rev 415 Rev 655
Line 160... Line 160...
   wire [31:0]                sram_flash_data;
   wire [31:0]                sram_flash_data;
   wire                      sram_flash_oe_n;
   wire                      sram_flash_oe_n;
   wire                      sram_flash_we_n;
   wire                      sram_flash_we_n;
   wire                      sram_mode;
   wire                      sram_mode;
`endif
`endif
 
`ifdef CFI_FLASH
 
   wire [15:0]        flash_dq_io;
 
   wire [23:0]        flash_adr_o;
 
   wire              flash_adv_n_o;
 
   wire              flash_ce_n_o;
 
   wire              flash_clk_o;
 
   wire              flash_oe_n_o;
 
   wire              flash_rst_n_o;
 
   wire              flash_wait_i;
 
   wire              flash_we_n_o;
 
`endif //  `ifdef CFI_FLASH
 
 
 
 
   orpsoc_top dut
   orpsoc_top dut
     (
     (
`ifdef JTAG_DEBUG
`ifdef JTAG_DEBUG
      .tms_pad_i                        (tms_pad_i),
      .tms_pad_i                        (tms_pad_i),
Line 196... Line 208...
      .sram_bw                          (sram_bw),
      .sram_bw                          (sram_bw),
      .sram_adv_ld_n                    (sram_adv_ld_n),
      .sram_adv_ld_n                    (sram_adv_ld_n),
      .sram_mode                        (sram_mode),
      .sram_mode                        (sram_mode),
      .sram_clk_fb                      (sram_clk_fb),
      .sram_clk_fb                      (sram_clk_fb),
      .sram_flash_data                  (sram_flash_data),
      .sram_flash_data                  (sram_flash_data),
 
`endif //  `ifdef XILINX_SSRAM
 
`ifdef CFI_FLASH
 
      .flash_dq_io                      (flash_dq_io),
 
      .flash_adr_o                      (flash_adr_o),
 
      .flash_adv_n_o                    (flash_adv_n_o),
 
      .flash_ce_n_o                     (flash_ce_n_o),
 
      .flash_clk_o                      (flash_clk_o),
 
      .flash_oe_n_o                     (flash_oe_n_o),
 
      .flash_rst_n_o                    (flash_rst_n_o),
 
      .flash_wait_i                     (flash_wait_i),
 
      .flash_we_n_o                     (flash_we_n_o),
`endif
`endif
`ifdef UART0
`ifdef UART0
      .uart0_stx_pad_o                  (uart0_stx_pad_o),
      .uart0_stx_pad_o                  (uart0_stx_pad_o),
      .uart0_srx_pad_i                  (uart0_srx_pad_i),
      .uart0_srx_pad_i                  (uart0_srx_pad_i),
      .uart0_stx_expheader_pad_o        (uart0_stx_pad_o),
      .uart0_stx_expheader_pad_o        (uart0_stx_pad_o),
Line 490... Line 513...
   reg vcd_go = 0;
   reg vcd_go = 0;
   always @(vcd_go)
   always @(vcd_go)
     begin
     begin
 
 
 `ifdef VCD_DELAY
 `ifdef VCD_DELAY
        #(`VCD_DELAY);
        #(`VCD_DELAY);/*#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
 
        #(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
 
        #(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
 
        #(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
 
        #(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
 
        #(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
 
        #(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
 
        #(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
 
        #(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
 
*/
 `endif
 `endif
 
 
        // Delay by x insns
        // Delay by x insns
 `ifdef VCD_DELAY_INSNS
 `ifdef VCD_DELAY_INSNS
        #10; // Delay until after the value becomes valid
        #10; // Delay until after the value becomes valid
Line 574... Line 606...
   // Loopback UART lines
   // Loopback UART lines
   assign uart0_srx_pad_i = uart0_stx_pad_o;
   assign uart0_srx_pad_i = uart0_stx_pad_o;
 
 
`endif //  `ifdef UART0
`endif //  `ifdef UART0
 
 
 
`ifdef CFI_FLASH
 
 
 
  wire [35:0] VCC;  // Supply Voltage
 
  wire [35:0] VCCQ; // Supply Voltage for I/O Buffers
 
  wire [35:0] VPP; // Optional Supply Voltage for Fast Program & Erase  
 
 
 
   wire       Info;      // Activate/Deactivate info device operation
 
   assign Info = 1;
 
   assign VCC = 36'd1700;
 
   assign VCCQ = 36'd1700;
 
   assign VPP = 36'd2000;
 
 
 
   x28fxxxp30 cfi_flash(flash_adr_o,
 
                        flash_dq_io,
 
                        flash_we_n_o,
 
                        flash_oe_n_o,
 
                        flash_ce_n_o,
 
                        flash_adv_n_o,
 
                        flash_clk_o,
 
                        flash_wait_i,
 
                        1'b1,
 
                        flash_rst_n_o,
 
                        VCC,
 
                        VCCQ,
 
                        VPP,
 
                        Info);
 
 
 
`endif //  `ifdef CFI_FLASH
 
 
endmodule // orpsoc_testbench
endmodule // orpsoc_testbench
 
 
// Local Variables:
// Local Variables:
// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")
// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")
// verilog-library-files:()
// verilog-library-files:()

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