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/// ////
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/// ////
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/// Julius Baxter, julius@opencores.org ////
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/// Julius Baxter, julius@opencores.org ////
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/// ////
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/// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2009, 2010, 2011 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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| Line 85... |
Line 85... |
wbs1_dat_o,
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wbs1_dat_o,
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wbs1_ack_o,
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wbs1_ack_o,
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wbs1_err_o,
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wbs1_err_o,
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wbs1_rty_o,
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wbs1_rty_o,
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// Slave three
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// Wishbone Slave interface
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wbs2_adr_i,
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wbs2_dat_i,
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wbs2_sel_i,
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wbs2_we_i,
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wbs2_cyc_i,
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wbs2_stb_i,
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wbs2_cti_i,
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wbs2_bte_i,
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wbs2_dat_o,
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wbs2_ack_o,
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wbs2_err_o,
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wbs2_rty_o,
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wb_clk,
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wb_clk,
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wb_rst
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wb_rst
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);
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);
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parameter wb_dat_width = 32;
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parameter wb_dat_width = 32;
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parameter wb_adr_width = 32;
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parameter wb_adr_width = 32;
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parameter wb_addr_match_width = 8;
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parameter wb_addr_match_width = 8;
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parameter slave0_adr = 8'hf0; // FLASH ROM
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parameter slave0_adr = 8'he0; // FLASH ROM
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parameter slave1_adr = 8'h00; // Main memory (SDRAM/FPGA SRAM)
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parameter slave1_adr = 8'h00; // Main memory (SDRAM/FPGA SRAM)
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parameter slave2_adr = 8'hf0; // External flash
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`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width
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`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width
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input wb_clk;
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input wb_clk;
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input wb_rst;
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input wb_rst;
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Line 165... |
input [wb_dat_width-1:0] wbs1_dat_o;
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input [wb_dat_width-1:0] wbs1_dat_o;
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input wbs1_ack_o;
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input wbs1_ack_o;
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input wbs1_err_o;
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input wbs1_err_o;
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input wbs1_rty_o;
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input wbs1_rty_o;
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wire [1:0] slave_sel; // One bit per slave
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// WB Slave 2
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output [wb_adr_width-1:0] wbs2_adr_i;
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output [wb_dat_width-1:0] wbs2_dat_i;
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output [3:0] wbs2_sel_i;
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output wbs2_we_i;
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output wbs2_cyc_i;
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output wbs2_stb_i;
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output [2:0] wbs2_cti_i;
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output [1:0] wbs2_bte_i;
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input [wb_dat_width-1:0] wbs2_dat_o;
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input wbs2_ack_o;
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input wbs2_err_o;
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input wbs2_rty_o;
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wire [2:0] slave_sel; // One bit per slave
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reg watchdog_err;
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reg watchdog_err;
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`ifdef ARBITER_IBUS_WATCHDOG
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`ifdef ARBITER_IBUS_WATCHDOG
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reg [`ARBITER_IBUS_WATCHDOG_TIMER_WIDTH:0] watchdog_timer;
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reg [`ARBITER_IBUS_WATCHDOG_TIMER_WIDTH:0] watchdog_timer;
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reg wbs0_rty_o_r;
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reg wbs0_rty_o_r;
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reg [wb_dat_width-1:0] wbs1_dat_o_r;
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reg [wb_dat_width-1:0] wbs1_dat_o_r;
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reg wbs1_ack_o_r;
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reg wbs1_ack_o_r;
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reg wbs1_err_o_r;
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reg wbs1_err_o_r;
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reg wbs1_rty_o_r;
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reg wbs1_rty_o_r;
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reg [wb_dat_width-1:0] wbs2_dat_o_r;
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reg wbs2_ack_o_r;
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reg wbs2_err_o_r;
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reg wbs2_rty_o_r;
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wire wbm_ack_i_pre_reg;
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wire wbm_ack_i_pre_reg;
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wbs0_rty_o_r <= wbs0_rty_o;
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wbs0_rty_o_r <= wbs0_rty_o;
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wbs1_dat_o_r <= wbs1_dat_o;
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wbs1_dat_o_r <= wbs1_dat_o;
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wbs1_ack_o_r <= wbs1_ack_o;
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wbs1_ack_o_r <= wbs1_ack_o;
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wbs1_err_o_r <= wbs1_err_o;
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wbs1_err_o_r <= wbs1_err_o;
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wbs1_rty_o_r <= wbs1_rty_o;
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wbs1_rty_o_r <= wbs1_rty_o;
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wbs2_dat_o_r <= wbs2_dat_o;
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wbs2_ack_o_r <= wbs2_ack_o;
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wbs2_err_o_r <= wbs2_err_o;
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wbs2_rty_o_r <= wbs2_rty_o;
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end // always @ (posedge wb_clk)
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end // always @ (posedge wb_clk)
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// Slave select
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// Slave select
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assign slave_sel[0] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] ==
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assign slave_sel[0] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] ==
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slave0_adr;
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slave0_adr;
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assign slave_sel[1] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] ==
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assign slave_sel[1] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] ==
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slave1_adr;
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slave1_adr;
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assign slave_sel[2] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] ==
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slave2_adr;
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// Slave out assigns
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// Slave out assigns
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assign wbs0_adr_i = wbm_adr_o_r;
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assign wbs0_adr_i = wbm_adr_o_r;
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assign wbs0_dat_i = wbm_dat_o_r;
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assign wbs0_dat_i = wbm_dat_o_r;
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assign wbs0_we_i = wbm_dat_o_r;
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assign wbs0_we_i = wbm_dat_o_r;
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assign wbs0_sel_i = wbm_sel_o_r;
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assign wbs0_sel_i = wbm_sel_o_r;
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Line 311... |
assign wbs1_cti_i = wbm_cti_o_r;
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assign wbs1_cti_i = wbm_cti_o_r;
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assign wbs1_bte_i = wbm_bte_o_r;
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assign wbs1_bte_i = wbm_bte_o_r;
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assign wbs1_cyc_i = wbm_cyc_o_r & slave_sel[1];
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assign wbs1_cyc_i = wbm_cyc_o_r & slave_sel[1];
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assign wbs1_stb_i = wbm_stb_o_r & slave_sel[1];
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assign wbs1_stb_i = wbm_stb_o_r & slave_sel[1];
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assign wbs2_adr_i = wbm_adr_o_r;
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assign wbs2_dat_i = wbm_dat_o_r;
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assign wbs2_we_i = wbm_dat_o_r;
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assign wbs2_sel_i = wbm_sel_o_r;
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assign wbs2_cti_i = wbm_cti_o_r;
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assign wbs2_bte_i = wbm_bte_o_r;
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assign wbs2_cyc_i = wbm_cyc_o_r & slave_sel[1];
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assign wbs2_stb_i = wbm_stb_o_r & slave_sel[1];
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// Master out assigns
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// Master out assigns
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// Don't care about none selected...
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// Don't care about none selected...
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assign wbm_dat_i = slave_sel[1] ? wbs1_dat_o_r :
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assign wbm_dat_i = slave_sel[2] ? wbs2_dat_o_r :
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slave_sel[1] ? wbs1_dat_o_r :
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wbs0_dat_o_r ;
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wbs0_dat_o_r ;
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assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o_r) |
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assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o_r) |
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(slave_sel[1] & wbs1_ack_o_r)
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(slave_sel[1] & wbs1_ack_o_r) |
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;
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(slave_sel[2] & wbs2_ack_o_r);
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assign wbm_err_i = (slave_sel[0] & wbs0_err_o_r) |
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assign wbm_err_i = (slave_sel[0] & wbs0_err_o_r) |
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(slave_sel[1] & wbs1_err_o_r) |
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(slave_sel[1] & wbs1_err_o_r) |
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(slave_sel[2] & wbs2_err_o_r) |
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watchdog_err;
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watchdog_err;
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assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o_r) |
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assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o_r) |
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(slave_sel[1] & wbs1_rty_o_r);
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(slave_sel[1] & wbs1_rty_o_r) |
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(slave_sel[2] & wbs2_rty_o_r);
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// Non-registered ack
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// Non-registered ack
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assign wbm_ack_i_pre_reg = (slave_sel[0] & wbs0_ack_o) |
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assign wbm_ack_i_pre_reg = (slave_sel[0] & wbs0_ack_o) |
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(slave_sel[1] & wbs1_ack_o);
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(slave_sel[1] & wbs1_ack_o) |
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(slave_sel[2] & wbs2_ack_o);
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`else // !`ifdef ARBITER_IBUS_REGISTERING
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`else // !`ifdef ARBITER_IBUS_REGISTERING
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// Slave select
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// Slave select
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assign slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] ==
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assign slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] ==
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slave0_adr;
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slave0_adr;
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assign slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] ==
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assign slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] ==
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slave1_adr;
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slave1_adr;
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assign slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] ==
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slave2_adr;
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// Slave out assigns
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// Slave out assigns
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assign wbs0_adr_i = wbm_adr_o;
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assign wbs0_adr_i = wbm_adr_o;
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assign wbs0_dat_i = wbm_dat_o;
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assign wbs0_dat_i = wbm_dat_o;
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assign wbs0_we_i = wbm_we_o;
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assign wbs0_we_i = wbm_we_o;
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assign wbs0_sel_i = wbm_sel_o;
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assign wbs0_sel_i = wbm_sel_o;
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Line 377... |
assign wbs1_cti_i = wbm_cti_o;
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assign wbs1_cti_i = wbm_cti_o;
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assign wbs1_bte_i = wbm_bte_o;
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assign wbs1_bte_i = wbm_bte_o;
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assign wbs1_cyc_i = wbm_cyc_o & slave_sel[1];
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assign wbs1_cyc_i = wbm_cyc_o & slave_sel[1];
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assign wbs1_stb_i = wbm_stb_o & slave_sel[1];
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assign wbs1_stb_i = wbm_stb_o & slave_sel[1];
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assign wbs2_adr_i = wbm_adr_o;
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assign wbs2_dat_i = wbm_dat_o;
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assign wbs2_we_i = wbm_we_o;
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assign wbs2_sel_i = wbm_sel_o;
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assign wbs2_cti_i = wbm_cti_o;
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assign wbs2_bte_i = wbm_bte_o;
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assign wbs2_cyc_i = wbm_cyc_o & slave_sel[2];
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assign wbs2_stb_i = wbm_stb_o & slave_sel[2];
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// Master out assigns
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// Master out assigns
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// Don't care about none selected...
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// Don't care about none selected...
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assign wbm_dat_i = slave_sel[1] ? wbs1_dat_o :
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assign wbm_dat_i = slave_sel[2] ? wbs2_dat_o :
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slave_sel[1] ? wbs1_dat_o :
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wbs0_dat_o ;
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wbs0_dat_o ;
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assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o) |
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assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o) |
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(slave_sel[1] & wbs1_ack_o);
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(slave_sel[1] & wbs1_ack_o) |
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(slave_sel[2] & wbs2_ack_o);
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assign wbm_err_i = (slave_sel[0] & wbs0_err_o) |
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assign wbm_err_i = (slave_sel[0] & wbs0_err_o) |
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(slave_sel[1] & wbs1_err_o) |
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(slave_sel[1] & wbs1_err_o) |
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(slave_sel[2] & wbs2_err_o) |
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watchdog_err;
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watchdog_err;
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assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o) |
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assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o) |
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(slave_sel[1] & wbs1_rty_o);
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(slave_sel[1] & wbs1_rty_o) |
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(slave_sel[2] & wbs2_rty_o);
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`endif
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`endif
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endmodule // arbiter_ibus
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endmodule // arbiter_ibus
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