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/*
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/*
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*
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*
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* Simple 8-bit wide GPIO module
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* Simple 24-bit wide GPIO module
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*
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*
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* Can be made wider as needed, but must be done manually.
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* Can be made wider as needed, but must be done manually.
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*
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*
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* First lot of bytes are the GPIO I/O regs
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* First lot of bytes are the GPIO I/O regs
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* Second lot are the direction registers
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* Second lot are the direction registers
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*
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*
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* Register mapping:
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* Register mapping:
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*
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*
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* For 8 GPIOs we would have
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* For 8 GPIOs we would have
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* adr 0: gpio data 7:0
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* adr 0: gpio data 7:0
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* adr 1: gpio dir 7:0
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*
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*
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* So for 24 GPIOs we would have
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* adr 0: gpio data 7:0
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* adr 1: gpio data 15:8
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* adr 1: gpio data 15:8
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* adr 2: gpio data 24:16
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* adr 2: gpio data 23:16
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* adr 3: gpio dir 7:0
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* adr 3: gpio dir 7:0
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* adr 4: gpio dir 15:8
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* adr 4: gpio dir 15:8
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* adr 5: gpio dir 24:16
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* adr 5: gpio dir 23:16
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*
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* Obviously any width where width%8!=0 you must skip the remainder of the byte
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* before starting the dir registers.
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*
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*
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* Backend pinout file needs to be updated for any GPIO width changes.
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* Backend pinout file needs to be updated for any GPIO width changes.
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*
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*
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*/
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*/
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wb_rty_o,
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wb_rty_o,
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gpio_io);
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gpio_io);
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parameter gpio_io_width = 8;
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parameter gpio_io_width = 24;
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parameter gpio_dir_reset_val = 0;
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parameter gpio_dir_reset_val = 0;
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parameter gpio_o_reset_val = 0;
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parameter gpio_o_reset_val = 0;
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assign gpio_io[i] = (gpio_dir[i]) ? gpio_o[i] : 1'bz;
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assign gpio_io[i] = (gpio_dir[i]) ? gpio_o[i] : 1'bz;
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assign gpio_i[i] = (gpio_dir[i]) ? gpio_o[i] : gpio_io[i];
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assign gpio_i[i] = (gpio_dir[i]) ? gpio_o[i] : gpio_io[i];
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end
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end
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endgenerate
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endgenerate
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// GPIO data out register
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// GPIO dir register
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always @(posedge wb_clk)
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always @(posedge wb_clk)
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if (wb_rst)
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if (wb_rst)
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gpio_dir <= 0; // All set to in at reset
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gpio_o <= 0; // All set to in at reset
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else if (wb_stb_i & wb_we_i)
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else if (wb_stb_i & wb_we_i)
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begin
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begin
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if (wb_adr_i == ((gpio_io_width/8)))
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if (wb_adr_i == 0)
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gpio_dir[7:0] <= wb_dat_i;
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gpio_o[7:0] <= wb_dat_i;
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/*
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if (wb_adr_i == 1)
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if (wb_adr_i == ((gpio_io_width/8)+1))
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gpio_o[15:8] <= wb_dat_i;
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gpio_dir[15:8] <= wb_dat_i;
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if (wb_adr_i == 2)
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if (wb_adr_i == ((gpio_io_width/8)+2))
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gpio_o[23:16] <= wb_dat_i;
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//gpio_dir[23:16] <= wb_dat_i;
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gpio_dir[21:16] <= wb_dat_i[5:0];
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*/
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/* Add appropriate address detection here for wider GPIO */
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/* Add appropriate address detection here for wider GPIO */
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end
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end
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// GPIO data out register
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// GPIO dir register
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always @(posedge wb_clk)
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always @(posedge wb_clk)
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if (wb_rst)
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if (wb_rst)
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gpio_o <= 0; // All set to in at reset
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gpio_dir <= 0; // All set to in at reset
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else if (wb_stb_i & wb_we_i)
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else if (wb_stb_i & wb_we_i)
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begin
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begin
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if (wb_adr_i == 0)
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if (wb_adr_i == ((gpio_io_width/8)))
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gpio_o[7:0] <= wb_dat_i;
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gpio_dir[7:0] <= wb_dat_i;
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/*
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if (wb_adr_i == ((gpio_io_width/8)+1))
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if (wb_adr_i == 1)
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gpio_dir[15:8] <= wb_dat_i;
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gpio_o[15:8] <= wb_dat_i;
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if (wb_adr_i == ((gpio_io_width/8)+2))
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if (wb_adr_i == 2)
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//gpio_dir[23:16] <= wb_dat_i;
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gpio_o[23:16] <= wb_dat_i;
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gpio_dir[21:16] <= wb_dat_i[5:0];
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*/
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/* Add appropriate address detection here for wider GPIO */
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/* Add appropriate address detection here for wider GPIO */
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end
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end
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// Register the gpio in signal
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// Register the gpio in signal
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always @(posedge wb_clk)
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always @(posedge wb_clk)
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begin
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begin
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// Data regs
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// Data regs
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if (wb_adr_i == 0)
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if (wb_adr_i == 0)
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wb_dat_o[7:0] <= gpio_i[7:0];
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wb_dat_o[7:0] <= gpio_i[7:0];
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/*
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if (wb_adr_i == 1)
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if (wb_adr_i == 1)
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wb_dat_o[7:0] <= gpio_i[15:8];
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wb_dat_o[7:0] <= gpio_i[15:8];
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if (wb_adr_i == 2)
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if (wb_adr_i == 2)
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wb_dat_o[7:0] <= gpio_i[23:16];
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wb_dat_o[7:0] <= gpio_i[23:16];
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*/
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/* Add appropriate address detection here for wider GPIO */
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/* Add appropriate address detection here for wider GPIO */
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// Direction regs
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// Direction regs
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if (wb_adr_i == 1)
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if (wb_adr_i == ((gpio_io_width/8)))
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wb_dat_o[7:0] <= gpio_dir[7:0];
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wb_dat_o[7:0] <= gpio_dir[7:0];
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/*
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if (wb_adr_i == ((gpio_io_width/8)+1))
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if (wb_adr_i == 4)
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wb_dat_o[7:0] <= gpio_dir[15:8];
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wb_dat_o[7:0] <= gpio_dir[15:8];
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if (wb_adr_i == ((gpio_io_width/8)+2))
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if (wb_adr_i == 5)
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wb_dat_o[7:0] <= gpio_dir[23:16];
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wb_dat_o[7:0] <= gpio_dir[23:16];
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*/
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/* Add appropriate address detection here for wider GPIO */
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/* Add appropriate address detection here for wider GPIO */
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end
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end
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