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Line 43... |
//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS
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//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS
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`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus
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`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus
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// Generic FIFO implementation - hopefully synthesizable with Synplify
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// Generic FIFO implementation - hopefully synthesizable with Synplify
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`define ETH_FIFO_GENERIC
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//`define ETH_FIFO_GENERIC
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// Ethernet implemented in Xilinx Chips (uncomment following lines)
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// Ethernet implemented in Xilinx Chips (uncomment following lines)
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// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
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`define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
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// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors
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// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors
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// Core is going to be implemented in Virtex FPGA and contains Virtex
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// Core is going to be implemented in Virtex FPGA and contains Virtex
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// specific elements.
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// specific elements.
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// Ethernet implemented in Altera Chips (uncomment following lines)
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// Ethernet implemented in Altera Chips (uncomment following lines)
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Line 184... |
// Settings for TX FIFO
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// Settings for TX FIFO
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`define ETH_TX_FIFO_DATA_WIDTH 32
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`define ETH_TX_FIFO_DATA_WIDTH 32
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// Defines for ethernet TX fifo size - impacts FPGA resource usage
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// Defines for ethernet TX fifo size - impacts FPGA resource usage
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//`define ETH_TX_FULL_PACKET_FIFO // Full 1500 byte TX buffer - uncomment this
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//`define ETH_TX_FULL_PACKET_FIFO // Full 1500 byte TX buffer - uncomment this
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//`define ETH_TX_256BYTE_FIFO // 256 byte TX buffer - uncomment this
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//`define ETH_TX_128BYTE_FIFO // 128 byte TX buffer - uncomment this
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`define ETH_TX_256BYTE_FIFO // 256 byte TX buffer - uncomment this
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//`define ETH_TX_512BYTE_FIFO // 512 byte TX buffer - uncomment this
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//`define ETH_TX_512BYTE_FIFO // 512 byte TX buffer - uncomment this
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`define ETH_TX_1KBYTE_FIFO // 1024 byte TX buffer - uncomment this
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//`define ETH_TX_1KBYTE_FIFO // 1024 byte TX buffer - uncomment this
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`ifdef ETH_TX_FULL_PACKET_FIFO
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`ifdef ETH_TX_FULL_PACKET_FIFO
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`define ETH_TX_FIFO_CNT_WIDTH 9
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`define ETH_TX_FIFO_CNT_WIDTH 9
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`define ETH_TX_FIFO_DEPTH 375
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`define ETH_TX_FIFO_DEPTH 375
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`else
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`else
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Line 205... |
`else
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`else
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`ifdef ETH_TX_256BYTE_FIFO
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`ifdef ETH_TX_256BYTE_FIFO
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`define ETH_TX_FIFO_CNT_WIDTH 6
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`define ETH_TX_FIFO_CNT_WIDTH 6
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`define ETH_TX_FIFO_DEPTH 64
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`define ETH_TX_FIFO_DEPTH 64
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`else
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`else
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`ifdef ETH_TX_128BYTE_FIFO
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`define ETH_TX_FIFO_CNT_WIDTH 5
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`define ETH_TX_FIFO_DEPTH 32
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`else
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// Default is 64 bytes
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// Default is 64 bytes
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`define ETH_TX_FIFO_CNT_WIDTH 4
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`define ETH_TX_FIFO_CNT_WIDTH 4
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`define ETH_TX_FIFO_DEPTH 16
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`define ETH_TX_FIFO_DEPTH 16
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`endif
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`endif
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`endif
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`endif
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`endif
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`endif // !`ifdef ETH_TX_512BYTE_FIFO
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`endif // !`ifdef ETH_TX_512BYTE_FIFO
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`endif // !`ifdef ETH_TX_FULL_PACKET_FIFO
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`endif // !`ifdef ETH_TX_FULL_PACKET_FIFO
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// Settings for RX FIFO
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// Settings for RX FIFO
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`define ETH_RX_FIFO_CNT_WIDTH 8
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//`define ETH_RX_FIFO_CNT_WIDTH 8
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`define ETH_RX_FIFO_DEPTH 256
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//`define ETH_RX_FIFO_DEPTH 256
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//`define ETH_RX_FIFO_CNT_WIDTH 7
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//`define ETH_RX_FIFO_CNT_WIDTH 7
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//`define ETH_RX_FIFO_DEPTH 128
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//`define ETH_RX_FIFO_DEPTH 128
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//`define ETH_RX_FIFO_CNT_WIDTH 6
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//`define ETH_RX_FIFO_CNT_WIDTH 6
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//`define ETH_RX_FIFO_DEPTH 64
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//`define ETH_RX_FIFO_DEPTH 64
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//`define ETH_RX_FIFO_CNT_WIDTH 5
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//`define ETH_RX_FIFO_CNT_WIDTH 5
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//`define ETH_RX_FIFO_DEPTH 32
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//`define ETH_RX_FIFO_DEPTH 32
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//`define ETH_RX_FIFO_CNT_WIDTH 4
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`define ETH_RX_FIFO_CNT_WIDTH 4
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//`define ETH_RX_FIFO_DEPTH 16
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`define ETH_RX_FIFO_DEPTH 16
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`define ETH_RX_FIFO_DATA_WIDTH 32
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`define ETH_RX_FIFO_DATA_WIDTH 32
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// Burst length
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// Burst length
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`define BURST_4BEAT
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`define BURST_4BEAT
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Line 245... |
//`define ETH_BURST_CNT_WIDTH 7 // The counter must be width enough to count to ETH_BURST_LENGTH
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//`define ETH_BURST_CNT_WIDTH 7 // The counter must be width enough to count to ETH_BURST_LENGTH
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// Undefine this to enable bursting for RX (writing to memory)
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// Undefine this to enable bursting for RX (writing to memory)
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`define ETH_RX_BURST_EN
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`define ETH_RX_BURST_EN
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// WISHBONE interface is Revision B3 compliant (uncomment when needed)
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// WISHBONE interface is Revision B3 compliant (uncomment when needed)
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`define ETH_WISHBONE_B3
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`define ETH_WISHBONE_B3
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// Hack where the transmit logic polls each of the TX buffers instead of having to keep track of what's going on
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// Hack where the transmit logic polls each of the TX buffers instead of having to keep track of what's going on
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//`define TXBD_POLL
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//`define TXBD_POLL
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// Define this to allow reading of the Wishbone control state machine on reg
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// Define this to allow reading of the Wishbone control state machine on reg
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// address 0x58
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// address 0x58
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`define WISHBONE_DEBUG
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No newline at end of file
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No newline at end of file
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//`define WISHBONE_DEBUG
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No newline at end of file
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No newline at end of file
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