| Line 160... |
Line 160... |
// Size/type of insn/data cache if implemented
|
// Size/type of insn/data cache if implemented
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// (consider available FPGA memory resources)
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// (consider available FPGA memory resources)
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//
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//
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//`define OR1200_IC_1W_512B
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//`define OR1200_IC_1W_512B
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//`define OR1200_IC_1W_4KB
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//`define OR1200_IC_1W_4KB
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`define OR1200_IC_1W_8KB
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//`define OR1200_IC_1W_8KB
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|
//`define OR1200_IC_1W_16KB
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`define OR1200_IC_1W_32KB
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//`define OR1200_DC_1W_4KB
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//`define OR1200_DC_1W_4KB
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`define OR1200_DC_1W_8KB
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//`define OR1200_DC_1W_8KB
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//`define OR1200_DC_1W_16KB
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`define OR1200_DC_1W_32KB
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|
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`endif
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`endif
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|
|
|
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//////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////
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| Line 347... |
Line 351... |
//
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//
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// Implement Find First/Last '1'
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// Implement Find First/Last '1'
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//
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//
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`define OR1200_IMPL_ALU_FFL1
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`define OR1200_IMPL_ALU_FFL1
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|
|
|
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//
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//
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// Implement multiplier
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// Implement multiplier
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//
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//
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// By default multiplier is implemented
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// By default multiplier is implemented
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//
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//
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| Line 464... |
Line 467... |
`define OR1200_ALUOP_SHROT 4'd8
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`define OR1200_ALUOP_SHROT 4'd8
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`define OR1200_ALUOP_DIV 4'd9
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`define OR1200_ALUOP_DIV 4'd9
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`define OR1200_ALUOP_DIVU 4'd10
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`define OR1200_ALUOP_DIVU 4'd10
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`define OR1200_ALUOP_MULU 4'd11
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`define OR1200_ALUOP_MULU 4'd11
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/* Values sent to ALU from decode unit - not strictly defined by ISA */
|
/* Values sent to ALU from decode unit - not strictly defined by ISA */
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`define OR1200_ALUOP_IMM 4'd11
|
|
`define OR1200_ALUOP_MOVHI 4'd12
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`define OR1200_ALUOP_MOVHI 4'd12
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`define OR1200_ALUOP_COMP 4'd13
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`define OR1200_ALUOP_COMP 4'd13
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`define OR1200_ALUOP_MTSR 4'd14
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`define OR1200_ALUOP_MTSR 4'd14
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`define OR1200_ALUOP_MFSR 4'd15
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`define OR1200_ALUOP_MFSR 4'd15
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`define OR1200_ALUOP_CMOV 4'd14
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`define OR1200_ALUOP_CMOV 4'd14
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| Line 1219... |
Line 1221... |
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
//
|
//
|
// Insn cache (IC)
|
// Insn cache (IC)
|
//
|
//
|
|
|
// 3 for 8 bytes, 4 for 16 bytes etc
|
// 4 for 16 byte line, 5 for 32 byte lines.
|
|
`ifdef OR1200_IC_1W_32KB
|
|
`define OR1200_ICLS 5
|
|
`else
|
`define OR1200_ICLS 4
|
`define OR1200_ICLS 4
|
|
`endif
|
|
|
//
|
//
|
// IC configurations
|
// IC configurations
|
//
|
//
|
`ifdef OR1200_IC_1W_512B
|
`ifdef OR1200_IC_1W_512B
|
| Line 1249... |
Line 1255... |
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12
|
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12
|
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13
|
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13
|
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9
|
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9
|
`define OR1200_ICTAG_W 20
|
`define OR1200_ICTAG_W 20
|
`endif
|
`endif
|
|
`ifdef OR1200_IC_1W_16KB
|
|
`define OR1200_ICSIZE 14 // 16384
|
|
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 12
|
|
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 13
|
|
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14
|
|
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10
|
|
`define OR1200_ICTAG_W 19
|
|
`endif
|
|
`ifdef OR1200_IC_1W_32KB
|
|
`define OR1200_ICSIZE 15 // 32768
|
|
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 13
|
|
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 14
|
|
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14
|
|
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10
|
|
`define OR1200_ICTAG_W 18
|
|
`endif
|
|
|
|
|
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
//
|
//
|
// Data cache (DC)
|
// Data cache (DC)
|
//
|
//
|
|
|
// 3 for 8 bytes, 4 for 16 bytes etc
|
// 4 for 16 bytes, 5 for 32 bytes
|
|
`ifdef OR1200_DC_1W_32KB
|
|
`define OR1200_DCLS 5
|
|
`else
|
`define OR1200_DCLS 4
|
`define OR1200_DCLS 4
|
|
`endif
|
|
|
// Define to enable default behavior of cache as write through
|
// Define to enable default behavior of cache as write through
|
// Turning this off enabled write back statergy
|
// Turning this off enabled write back statergy
|
//
|
//
|
`define OR1200_DC_WRITETHROUGH
|
`define OR1200_DC_WRITETHROUGH
|
| Line 1297... |
Line 1323... |
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12
|
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12
|
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
|
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
|
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
|
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
|
`define OR1200_DCTAG_W 20
|
`define OR1200_DCTAG_W 20
|
`endif
|
`endif
|
|
`ifdef OR1200_DC_1W_16KB
|
|
`define OR1200_DCSIZE 14 // 16384
|
|
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 12
|
|
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 13
|
|
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 14
|
|
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10
|
|
`define OR1200_DCTAG_W 19
|
|
`endif
|
|
`ifdef OR1200_DC_1W_32KB
|
|
`define OR1200_DCSIZE 15 // 32768
|
|
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 13
|
|
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 14
|
|
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 15
|
|
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10
|
|
`define OR1200_DCTAG_W 18
|
|
`endif
|
|
|
|
|
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
//
|
//
|
// Store buffer (SB)
|
// Store buffer (SB)
|
