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Line 72... |
//`define ARBITER_IBUS_REGISTERING
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//`define ARBITER_IBUS_REGISTERING
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`define ARBITER_IBUS_WATCHDOG
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`define ARBITER_IBUS_WATCHDOG
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// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles
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// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles
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// This has to be kind of long, as DDR2 initialisation can take a little while
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// This has to be kind of long, as DDR2 initialisation can take a little while
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// and after reset, and if this is too short we'll always get bus error.
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// and after reset, and if this is too short we'll always get bus error.
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`ifdef XILINX_DDR2
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`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 20
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`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 20
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`else
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`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 6
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`endif
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// Data bus arbiter
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// Data bus arbiter
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//`define ARBITER_DBUS_REGISTERING
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//`define ARBITER_DBUS_REGISTERING
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`define ARBITER_DBUS_WATCHDOG
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`define ARBITER_DBUS_WATCHDOG
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// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles
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// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles
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`ifdef XILINX_DDR2
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`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 20
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`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 20
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`else
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`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 6
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`endif
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// Byte bus (peripheral bus) arbiter
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// Byte bus (peripheral bus) arbiter
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// Don't really need the watchdog here - the databus will pick it up
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// Don't really need the watchdog here - the databus will pick it up
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//`define ARBITER_BYTEBUS_WATCHDOG
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//`define ARBITER_BYTEBUS_WATCHDOG
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// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles
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// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles
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