OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [include/] [uart_defines.v] - Diff between revs 412 and 496

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 412 Rev 496
Line 244... Line 244...
// 115200 baud preset values
// 115200 baud preset values
// 20MHz: prescaler 10.8 (11, rounded up)
// 20MHz: prescaler 10.8 (11, rounded up)
//`define PRESCALER_HIGH_PRESET 8'd0
//`define PRESCALER_HIGH_PRESET 8'd0
//`define PRESCALER_LOW_PRESET 8'd11
//`define PRESCALER_LOW_PRESET 8'd11
// 50MHz: prescaler 27.1
// 50MHz: prescaler 27.1
 
//`define PRESCALER_HIGH_PRESET 8'd0
 
//`define PRESCALER_LOW_PRESET 8'd27
 
// 66MHz: prescaler 36.1
`define PRESCALER_HIGH_PRESET 8'd0
`define PRESCALER_HIGH_PRESET 8'd0
`define PRESCALER_LOW_PRESET 8'd27
`define PRESCALER_LOW_PRESET 8'd36
 
 
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.