URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [include/] [uart_defines.v] - Diff between revs 496 and 502

Rev 496	Rev 502
Line 238...	Line 238...
`define VERBOSE_WB 0 // All activity on the WISHBONE is recorded	`define VERBOSE_WB 0 // All activity on the WISHBONE is recorded
`define VERBOSE_LINE_STATUS 0 // Details about the lsr (line status register)	`define VERBOSE_LINE_STATUS 0 // Details about the lsr (line status register)
`define FAST_TEST 1 // 64/1024 packets are sent	`define FAST_TEST 1 // 64/1024 packets are sent

`// Defines hard baud prescaler register - uncomment to enable`	`// Defines hard baud prescaler register - uncomment to enable`
`define PRESCALER_PRESET_HARD	//`define PRESCALER_PRESET_HARD
`// 115200 baud preset values`	`// 115200 baud preset values`
`// 20MHz: prescaler 10.8 (11, rounded up)`	`// 20MHz: prescaler 10.8 (11, rounded up)`
//`define PRESCALER_HIGH_PRESET 8'd0	//`define PRESCALER_HIGH_PRESET 8'd0
//`define PRESCALER_LOW_PRESET 8'd11	//`define PRESCALER_LOW_PRESET 8'd11
`// 50MHz: prescaler 27.1`	`// 50MHz: prescaler 27.1`
//`define PRESCALER_HIGH_PRESET 8'd0	//`define PRESCALER_HIGH_PRESET 8'd0
//`define PRESCALER_LOW_PRESET 8'd27	//`define PRESCALER_LOW_PRESET 8'd27
`// 66MHz: prescaler 36.1`	`// 66MHz: prescaler 36.1`
`define PRESCALER_HIGH_PRESET 8'd0	//`define PRESCALER_HIGH_PRESET 8'd0
`define PRESCALER_LOW_PRESET 8'd36	//`define PRESCALER_LOW_PRESET 8'd36


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