| Line 53... |
Line 53... |
`ifdef UART0
|
`ifdef UART0
|
uart0_srx_pad_i, uart0_stx_pad_o,
|
uart0_srx_pad_i, uart0_stx_pad_o,
|
uart0_srx_expheader_pad_i, uart0_stx_expheader_pad_o,
|
uart0_srx_expheader_pad_i, uart0_stx_expheader_pad_o,
|
`endif
|
`endif
|
`ifdef SPI0
|
`ifdef SPI0
|
spi0_sck_o, spi0_mosi_o, spi0_miso_i, spi0_ss_o,
|
spi0_mosi_o, spi0_ss_o,/* spi0_sck_o, spi0_miso_i,via STARTUP_VIRTEX5*/
|
`endif
|
`endif
|
`ifdef I2C0
|
`ifdef I2C0
|
i2c0_sda_io, i2c0_scl_io,
|
i2c0_sda_io, i2c0_scl_io,
|
`endif
|
`endif
|
`ifdef I2C1
|
`ifdef I2C1
|
| Line 131... |
Line 131... |
// Duplicates of the UART signals, this time to the USB debug cable
|
// Duplicates of the UART signals, this time to the USB debug cable
|
input uart0_srx_expheader_pad_i;
|
input uart0_srx_expheader_pad_i;
|
output uart0_stx_expheader_pad_o;
|
output uart0_stx_expheader_pad_o;
|
`endif
|
`endif
|
`ifdef SPI0
|
`ifdef SPI0
|
output spi0_sck_o;
|
|
output spi0_mosi_o;
|
output spi0_mosi_o;
|
output [spi0_ss_width-1:0] spi0_ss_o;
|
output [spi0_ss_width-1:0] spi0_ss_o;
|
input spi0_miso_i;
|
/* via STARTUP_VIRTEX5
|
|
output spi0_sck_o;
|
|
input spi0_miso_i;
|
|
*/
|
`endif
|
`endif
|
`ifdef I2C0
|
`ifdef I2C0
|
inout i2c0_sda_io, i2c0_scl_io;
|
inout i2c0_sda_io, i2c0_scl_io;
|
`endif
|
`endif
|
`ifdef I2C1
|
`ifdef I2C1
|
| Line 1225... |
Line 1227... |
//
|
//
|
assign wbs_d_uart0_err_o = 0;
|
assign wbs_d_uart0_err_o = 0;
|
assign wbs_d_uart0_rty_o = 0;
|
assign wbs_d_uart0_rty_o = 0;
|
|
|
// Two UART lines coming to single one (ensure they go high when unconnected)
|
// Two UART lines coming to single one (ensure they go high when unconnected)
|
assign uart_srx = uart0_srx_pad_i & uart0_srx_expheader_pad_i;
|
assign uart0_srx = uart0_srx_pad_i & uart0_srx_expheader_pad_i;
|
assign uart0_stx_pad_o = uart0_stx;
|
assign uart0_stx_pad_o = uart0_stx;
|
assign uart0_stx_expheader_pad_o = uart0_stx;
|
assign uart0_stx_expheader_pad_o = uart0_stx;
|
|
|
|
|
uart16550 uart16550_0
|
uart16550 uart16550_0
|
| Line 1314... |
Line 1316... |
.miso_i (spi0_miso_i)
|
.miso_i (spi0_miso_i)
|
);
|
);
|
|
|
defparam spi0.slave_select_width = spi0_ss_width;
|
defparam spi0.slave_select_width = spi0_ss_width;
|
|
|
|
// SPI clock and MISO lines must go through STARTUP_VIRTEX5 block.
|
|
STARTUP_VIRTEX5 startup_virtex5
|
|
(
|
|
.CFGCLK(),
|
|
.CFGMCLK(),
|
|
.DINSPI(spi0_miso_i),
|
|
.EOS(),
|
|
.TCKSPI(),
|
|
.CLK(),
|
|
.GSR(1'b0),
|
|
.GTS(1'b0),
|
|
.USRCCLKO(spi0_sck_o),
|
|
.USRCCLKTS(1'b0),
|
|
.USRDONEO(),
|
|
.USRDONETS()
|
|
);
|
|
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
`else // !`ifdef SPI0
|
`else // !`ifdef SPI0
|
|
|
//
|
//
|
// Assigns
|
// Assigns
|
