OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [orpsoc_top/] [orpsoc_top.v] - Diff between revs 439 and 530

Show entire file | Details | Blame | View Log

Rev 439 Rev 530
Line 112... Line 112...
   output [1:0]        ddr2_ck;
   output [1:0]        ddr2_ck;
   output [1:0]        ddr2_ck_n;
   output [1:0]        ddr2_ck_n;
`endif
`endif
`ifdef XILINX_SSRAM
`ifdef XILINX_SSRAM
   // ZBT SSRAM
   // ZBT SSRAM
    output         sram_clk,
    output         sram_clk;
    input          sram_clk_fb,
    input          sram_clk_fb;
    output [21:1]  sram_flash_addr,
    output [21:1]  sram_flash_addr;
    inout [31:0]   sram_flash_data,
    inout [31:0]   sram_flash_data;
    output         sram_cen,
    output         sram_cen;
    output         sram_flash_oe_n,
    output         sram_flash_oe_n;
    output         sram_flash_we_n,
    output         sram_flash_we_n;
    output [3:0]   sram_bw,
    output [3:0]   sram_bw;
    output         sram_adv_ld_n,
    output         sram_adv_ld_n;
    output         sram_mode,
    output         sram_mode;
`endif
`endif
`ifdef UART0
`ifdef UART0
   input         uart0_srx_pad_i;
   input         uart0_srx_pad_i;
   output        uart0_stx_pad_o;
   output        uart0_stx_pad_o;
   // Duplicates of the UART signals, this time to the USB debug cable
   // Duplicates of the UART signals, this time to the USB debug cable

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.