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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [xilinx_ddr2/] [ddr2_ctrl.v] - Diff between revs 412 and 480

Rev 412	Rev 480
Line 345...	Line 345...
`// be set the cycle af_valid_r is de-asserted.`	`// be set the cycle af_valid_r is de-asserted.`
`always @(posedge clk) begin`	`always @(posedge clk) begin`
`// for simulation purposes - to force CTRL_AF_RDEN low during reset`	`// for simulation purposes - to force CTRL_AF_RDEN low during reset`
`if (rst_r1)`	`if (rst_r1)`
`rd_af_flag_r <= 1'd0;`	`rd_af_flag_r <= 1'd0;`
`else if (rd_af_flag_r) // jb - probably should find a way to stop this toggling all the time`	`else if (rd_af_flag_r) // jb - probably should find a way`
	`// to stop this toggling all the time`
`rd_af_flag_r <= 0; // jb`	`rd_af_flag_r <= 0; // jb`
`else if((ctrl_af_rden_r) \|\|`	`else if((ctrl_af_rden_r) \|\|`
`(/rd_af_flag_r &&/ (af_valid_r \|\| af_valid_r1))) // Fixed bug where third addresses would get lost (pulled off fifo and then clobbered by other value later, thus ignored/skipped) - just make sure we don't get too excited and pull too many off at once - jb`	`(/rd_af_flag_r &&/ (af_valid_r \|\| af_valid_r1)))`
	`// Fixed bug where third addresses would get lost (pulled off fifo and`
	`// then clobbered by other value later, thus ignored/skipped) - just`
	`// make sure we don't get too excited and pull too many off at once - jb`
`rd_af_flag_r <= 1'd0;`	`rd_af_flag_r <= 1'd0;`
`else if (~af_valid_r1 \|\| ~af_valid_r)`	`else if (~af_valid_r1 \|\| ~af_valid_r)`
`rd_af_flag_r <= 1'd1;`	`rd_af_flag_r <= 1'd1;`

`end // always @ (posedge clk)`	`end // always @ (posedge clk)`