OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [xilinx_ddr2/] [xilinx_ddr2.v] - Diff between revs 412 and 439

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 412	Rev 439
Line 179...	Line 179...

`.wb_dat_o (wbs_ram_dat_o),`	`.wb_dat_o (wbs_ram_dat_o),`
`.wb_ack_o (wbs_ram_ack_o),`	`.wb_ack_o (wbs_ram_ack_o),`
`.wb_adr_i (wbs_ram_adr_i[31:0]),`	`.wb_adr_i (wbs_ram_adr_i[31:0]),`
`.wb_stb_i (wbs_ram_stb_i),`	`.wb_stb_i (wbs_ram_stb_i),`
	`.wb_cti_i (wbs_ram_cti_i),`
	`.wb_bte_i (wbs_ram_bte_i),`
`.wb_cyc_i (wbs_ram_cyc_i),`	`.wb_cyc_i (wbs_ram_cyc_i),`
`.wb_we_i (wbs_ram_we_i),`	`.wb_we_i (wbs_ram_we_i),`
`.wb_sel_i (wbs_ram_sel_i[3:0]),`	`.wb_sel_i (wbs_ram_sel_i[3:0]),`
`.wb_dat_i (wbs_ram_dat_i[31:0]),`	`.wb_dat_i (wbs_ram_dat_i[31:0]),`

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.