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| Rev 412 |
Rev 439 |
| Line 102... |
Line 102... |
*/
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*/
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module xilinx_ddr2_if (
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module xilinx_ddr2_if (
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input [31:0] wb_adr_i,
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input [31:0] wb_adr_i,
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input wb_stb_i,
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input wb_stb_i,
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input wb_cyc_i,
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input wb_cyc_i,
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input [2:0] wb_cti_i,
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input [1:0] wb_bte_i,
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input wb_we_i,
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input wb_we_i,
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input [3:0] wb_sel_i,
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input [3:0] wb_sel_i,
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input [31:0] wb_dat_i,
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input [31:0] wb_dat_i,
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output [31:0] wb_dat_o,
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output [31:0] wb_dat_o,
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output reg wb_ack_o,
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output reg wb_ack_o,
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wire [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data;
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wire [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data;
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wire rd_data_valid;
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wire rd_data_valid;
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wire [(APPDATA_WIDTH)-1:0] rd_data_fifo_out;
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wire [(APPDATA_WIDTH)-1:0] rd_data_fifo_out;
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wire phy_init_done;
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wire phy_init_done;
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assign cache_hit = (cached_addr == wb_adr_i[31:6]) & cached_addr_valid;
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assign cache_hit = (cached_addr == wb_adr_i[31:6]) & cached_addr_valid;
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// Wishbone request detection
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// Wishbone request detection
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assign wb_req = wb_stb_i & wb_cyc_i & phy_init_done;
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assign wb_req = wb_stb_i & wb_cyc_i & phy_init_done;
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// Read done signaling to WB domain
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// Read done signaling to WB domain
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always @(posedge ddr2_clk)
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always @(posedge ddr2_clk)
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if (ddr2_rst)
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if (ddr2_rst)
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ddr2_read_done <= 0;
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ddr2_read_done <= 0;
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else if (!rd_data_valid & rd_data_valid_r) // Detect read data valid falling edge
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// Detect read data valid falling edge
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else if (!rd_data_valid & rd_data_valid_r)
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ddr2_read_done <= 1;
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ddr2_read_done <= 1;
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else if (!(|ddr2_clk_phase) & !do_readfrom) // Read WB domain
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else if (!(|ddr2_clk_phase) & !do_readfrom) // Read WB domain
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ddr2_read_done <= 0;
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ddr2_read_done <= 0;
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wire [3:0] wb_cache_adr;
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wire [3:0] wb_cache_adr;
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