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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Xilinx DDR2 controller Wishbone Interface ////
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//// Xilinx ML501 DDR2 controller Wishbone Interface ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Simple interface to the Xilinx MIG generated DDR2 controller////
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//// Simple interface to the Xilinx MIG generated DDR2 controller////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Increase usage of cache BRAM to maximum (currently only ////
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//// Use full capacity of BRAM ////
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//// 256 bytes out of about 8192) ////
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//// Employ LRU replacement scheme ////
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//// Make this a Wishbone B3 registered feedback burst friendly ////
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//// Remove hard-coding of things relating to number of lines ////
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//// server. ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Julius Baxter, julius.baxter@orsoc.se ////
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//// - Julius Baxter, julius.baxter@orsoc.se ////
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//// ////
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//// ////
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//// ////
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//// ////
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| Line 40... |
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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/*
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/*
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* The controller is design to stream lots of data out at the DDR2 controller's
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* This is an interface to the Xilinx MIG-sourced DDR2 controller.
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* rate. All we implement here is enough to do the simplest accesses into a
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*
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* small cache, which eases the domain crossing headaches.
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* The controller's interface is via FIFO buffers - one for address and control
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*
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* the other is for data. The data FIFO interface is 128-bits wide.
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* This was originally written to handle a DDR2 part which is doing burst length
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*
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* of 4 as a minimum via a databus which is 64-bits wide.
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* This module has a cache with different aspects on each port. As we're to
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*
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* ultimately interface to a 32-bit wide Wishbone bus, one side is 32-bits
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* This means the smallest accesses is 4*64=256-bits or 32-bytes.
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* and the other is 128-bits wide to accommodate the DDR2 controller's data
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*
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* path.
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* We are bridging to a 32-bit wide system bus, so this means we must handle
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*
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* accesses in 8-word lots.
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* At present, the cache controller doesn't employ associativity, so any
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*
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* line can be used for any location. A round-robin approach to line
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* A simple cache mechanism has been implemented, meaning we check if the cached
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* use is employed. TODO is LRU scheme instead of round robin.
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* data has been written to, and therefore needs writing back to the main memory
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*
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* before any other access can occur.
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* The cache is a macro generated by Xilinx's IP generation tool. This is
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*
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* because memories with dual-aspect ratios cannot be inferred via HDL.
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* Cache memory:
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*
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* The cache memory is a core-generated module, instantiating something out
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* The size of lines, as set by the defines, controls how long each read
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* of the XilinxCoreLib. The reason is because an arrangement or RAMB36s with
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* and write burst to/from the SDRAM is.
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* different sized A and B data in/out ports can't be instantiated directly
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*
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* for some reason.
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* There are two clock domains - the Wishbone and the DDR2 controller domain.
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* What we have is side A with 32-bits, and side B with 128-bits wide.
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*
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*
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* A signal is sent to control logic in the DDR2 domain side to load and store
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* TODO:
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* the contents of a particular line from and to the DDR2 controller's data
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* This only supports 8-words for now but can easily be expanded, although
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* FIFOs. This loading and storing is done at the DDR2 clock domain's rate.
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* multiple way/associativity caching will require some extra work to handle
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*
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* multiple cached addresses.
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* The writing of address and control data is done from the Wishbone domain.
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*
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* But it should be easy enough to make this thing cache as much as its RAMB
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* resources allow (4-RAMB16s becuase due to the 128-bit DDR2-side interface)
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* which is about 8Kbyte.
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*
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*
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* Multi-cycle paths:
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* Multi-cycle paths:
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* Write:
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* Write:
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* To indicate that a writeback is occuring, a system-bus domain (wishbone, in
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* To indicate that a writeback is occuring, a system-bus domain (wishbone, in
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* this case) signal is set, and then sampled in the controller domain whenever
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* this case) signal is set, and then sampled in the controller domain whenever
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| Line 82... |
Line 77... |
* and then the controller domain register "ddr2_write_done" is asserted when
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* and then the controller domain register "ddr2_write_done" is asserted when
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* the data has been written out of the RAMs and into the controller's fifos.
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* the data has been written out of the RAMs and into the controller's fifos.
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* "ddr2_write_done" is then sampled by the system-bus domain and "do_writeback"
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* "ddr2_write_done" is then sampled by the system-bus domain and "do_writeback"
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* So there are paths between:
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* So there are paths between:
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* ( register -> (sampled by) -> register )
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* ( register -> (sampled by) -> register )
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* wb_clk:do_writeback -> ddr2_clk:do_writeback_ddr2_shifter
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* wb_clk:do_writeback -> ddr2_clk:do_writeback_ddr2
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* wb_clk:do_writeback -> ddr2_clk:ddr2_write_done
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* wb_clk:do_writeback -> ddr2_clk:ddr2_write_done
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* ddr2_clk:ddr2_write_done -> wb_clk:do_writeback
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* ddr2_clk:ddr2_write_done -> wb_clk:do_writeback
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*
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*
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* Read:
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* Read:
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* The only signal crossing we have here is the one indicating the read data
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* The only signal crossing we have here is the one indicating the read data
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| Line 98... |
Line 93... |
* ( register -> (sampled by) -> register )
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* ( register -> (sampled by) -> register )
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* ddr2_clk:ddr2_read_done -> wb_clk:do_readfrom
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* ddr2_clk:ddr2_read_done -> wb_clk:do_readfrom
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* wb_clk:do_readfrom -> ddr2_clk:ddr2_read_done
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* wb_clk:do_readfrom -> ddr2_clk:ddr2_read_done
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*
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*
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*/
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*/
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module xilinx_ddr2_if (
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module xilinx_ddr2_if2 (
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input [31:0] wb_adr_i,
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input [31:0] wb_adr_i,
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input wb_stb_i,
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input wb_stb_i,
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input wb_cyc_i,
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input wb_cyc_i,
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input [2:0] wb_cti_i,
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input [2:0] wb_cti_i,
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input [1:0] wb_bte_i,
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input [1:0] wb_bte_i,
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| Line 129... |
Line 124... |
output [1:0] ddr2_ck_n,
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output [1:0] ddr2_ck_n,
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|
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input ddr2_if_clk,
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input ddr2_if_clk,
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input ddr2_if_rst,
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input ddr2_if_rst,
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input idly_clk_200,
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input idly_clk_200,
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input wb_clk,
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input wb_clk,
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input wb_rst);
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input wb_rst);
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`include "xilinx_ddr2_params.v"
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`include "xilinx_ddr2_params.v"
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// Define to add a counter, signaling error if the controller locks up
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// (no ack after a certain period of time)
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//`define ERR_COUNTER
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/*
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`define DDR2_CACHE_NUM_LINES 16
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`define DDR2_CACHE_NUM_LINES_ENC_WIDTH 4 // log2(`DDR2_CACHE_NUM_LINES)
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*/
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`define DDR2_CACHE_NUM_LINES 4
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`define DDR2_CACHE_NUM_LINES_ENC_WIDTH 2 // log2(`DDR2_CACHE_NUM_LINES)
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`define DDR2_CACHE_NUM_WORDS_PER_LINE 256
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`define DDR2_CACHE_ADDR_WIDTH_WORDS_PER_LINE 8
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`define DDR2_CACHE_TAG_ADDR_WIDTH (32-`DDR2_CACHE_ADDR_WIDTH_WORDS_PER_LINE-2)
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`define DDR2_CACHE_DDR2_SIDE_NUM_WORDS_PER_LINE (`DDR2_CACHE_NUM_WORDS_PER_LINE/4)
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`define DDR2_CACHE_DDR2_SIDE_ADDR_WIDTH_NUM_WORDS_PER_LINE (`DDR2_CACHE_ADDR_WIDTH_WORDS_PER_LINE - 2)
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`define DDR2_CACHE_DDR2_SIDE_ADDR_WIDTH (`DDR2_CACHE_NUM_LINES_ENC_WIDTH + `DDR2_CACHE_DDR2_SIDE_ADDR_WIDTH_NUM_WORDS_PER_LINE)
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`define DDR2_CACHE_TAG_BITS 31:(`DDR2_CACHE_ADDR_WIDTH_WORDS_PER_LINE+2)
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wire ddr2_clk; // DDR2 iface domain clock.
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wire ddr2_clk; // DDR2 iface domain clock.
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wire ddr2_rst; // reset from the ddr2 module
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wire ddr2_rst; // reset from the ddr2 module
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wire wb_req;
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wire wb_req;
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reg wb_req_r;
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reg wb_req_r;
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reg wb_ack_o_r;
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reg wb_ack_o_r;
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wire wb_req_new;
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wire wb_req_new;
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reg wb_req_new_r;
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reg wb_req_new_r;
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reg wb_req_addr_hit;
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wire wb_req_addr_hit;
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reg cached_addr_valid;
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wire cached_addr_valid;
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reg [31:6] cached_addr;
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wire cache_hit;
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wire [31:(32 -`DDR2_CACHE_TAG_ADDR_WIDTH)] cached_addr;
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`define DDR2_BURST_8_DQ64_ADDR_WIDTH 4 // = log2(burst of 8 64-bits = 16 words)
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`define DDR2_BURST_4_DQ64_ADDR_WIDTH 3 // = log2(burst of 4 64-bits = 8 words)
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// This counts how many addresses we should write to the fifo - the number
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// of discrete FIFO transactions.
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reg [`DDR2_CACHE_ADDR_WIDTH_WORDS_PER_LINE-`DDR2_BURST_8_DQ64_ADDR_WIDTH - 1:0] addr_counter;
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reg cache_dirty;
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wire cache_write;
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reg [2:0] wb_req_cache_word_addr;
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wire cache_hit;
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wire wb_cache_en;
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wire wb_cache_en;
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reg do_writeback, do_writeback_r;
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reg do_writeback, do_writeback_r;
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wire do_writeback_start, do_writeback_finished;
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wire do_writeback_start, do_writeback_finished;
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wire doing_writeback;
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// Wire to indicate writing to data FIFO of MIG has completed
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wire do_writeback_data_finished;
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// Wire to indicate that address FIFO of MIG should be written to to
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// initiate memory accesses.
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reg do_writeback_addresses, do_writeback_addresses_r;
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reg do_readfrom, do_readfrom_r;
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reg do_readfrom, do_readfrom_r;
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wire do_readfrom_start, do_readfrom_finished;
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wire do_readfrom_start, do_readfrom_finished;
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wire doing_readfrom;
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wire doing_readfrom;
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reg do_af_write;
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// Domain crossing logic
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// Domain crossing logic
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reg wb_clk_r;
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reg wb_clk_r;
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reg wb_clk_in_ddr2_clk;
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reg wb_clk_in_ddr2_clk;
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reg wb_clk_in_ddr2_clk_r;
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reg wb_clk_in_ddr2_clk_r;
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wire wb_clk_edge;
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wire wb_clk_edge;
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reg [2:0] ddr2_clk_phase;
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reg [2:0] ddr2_clk_phase;
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// Sample when clk phase is 0
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// Sample when clk phase is 0
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reg [7:0] do_writeback_ddr2_shifter;
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reg do_writeback_ddr2;
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reg [7:0] do_writeback_ddr2_shifter_r;
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reg do_writeback_ddr2_fifo_we;
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reg do_writeback_ddr2_fifo_we;
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reg ddr2_write_done;
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reg ddr2_write_done;
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reg [`DDR2_CACHE_DDR2_SIDE_ADDR_WIDTH_NUM_WORDS_PER_LINE - 1:0] ddr2_cache_line_word_addr;
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// Currently, ddr2-side of cache is address is a single bit
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reg [1:0] ddr2_cache_addr;
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wire [127:0] ddr2_cache_data_o;
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wire [127:0] ddr2_cache_data_o;
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reg rd_data_valid_r;
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reg rd_data_valid_r;
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reg ddr2_read_done;
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reg ddr2_read_done;
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// DDR2 MIG interface wires
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// DDR2 MIG interface wires
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wire app_af_afull;
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wire app_af_afull;
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wire app_wdf_afull;
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wire app_wdf_afull;
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wire app_wdf_wren;
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wire app_wdf_wren;
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wire app_af_wren;
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wire app_af_wren;
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wire [30:0] writeback_af_addr;
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wire [30:0] readfrom_af_addr;
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wire [30:0] app_af_addr;
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wire [30:0] app_af_addr;
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wire [2:0] app_af_cmd;
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wire [2:0] app_af_cmd;
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|
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wire [(APPDATA_WIDTH)-1:0] app_wdf_data;
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wire [(APPDATA_WIDTH)-1:0] app_wdf_data;
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wire [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data;
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wire [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data;
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wire rd_data_valid;
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wire rd_data_valid;
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wire [(APPDATA_WIDTH)-1:0] rd_data_fifo_out;
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wire [(APPDATA_WIDTH)-1:0] rd_data_fifo_out;
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wire phy_init_done;
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wire phy_init_done;
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|
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assign cache_hit = (cached_addr == wb_adr_i[31:6]) & cached_addr_valid;
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wire [`DDR2_CACHE_NUM_LINES - 1 :0] cache_line_addr_validate;
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wire [`DDR2_CACHE_NUM_LINES - 1 :0] cache_line_addr_invalidate;
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wire [`DDR2_CACHE_NUM_LINES - 1 :0] cache_line_addr_valid;
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wire [`DDR2_CACHE_NUM_LINES - 1 :0] cache_line_hit;
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wire [`DDR2_CACHE_TAG_BITS] cache_line_addr [0:`DDR2_CACHE_NUM_LINES-1] ;
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// Cache control signals
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// Wishbone side
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wire [`DDR2_CACHE_ADDR_WIDTH_WORDS_PER_LINE-1:0] wb_cache_adr;
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wire [3:0] wb_cache_sel_we;
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// DDR side
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wire ddr2_cache_en;
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wire [15:0] ddr2_cache_we;
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reg wb_bursting; // Indicate if burst is enabled
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reg [3:0] wb_burst_addr; // Burst counter, up to 16
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wire [1:0] wb_burst_addr_4beat;
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wire [2:0] wb_burst_addr_8beat;
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wire wb_burst_addr_incr;
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wire ack_err;
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reg ack_err_r;
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// Decoded select line
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wire [`DDR2_CACHE_NUM_LINES-1:0] selected_cache_line;
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wire [`DDR2_CACHE_NUM_LINES_ENC_WIDTH-1:0] selected_cache_line_enc;
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reg [`DDR2_CACHE_NUM_LINES_ENC_WIDTH-1:0] selected_cache_line_enc_ddr2_clk;
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|
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genvar i;
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generate
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for (i=0;i<`DDR2_CACHE_NUM_LINES;i=i+1) begin : cache_addr
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xilinx_ddr2_wb_if_cache_adr_reg cache_addr_reg_inst
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( .adr_i(wb_adr_i[`DDR2_CACHE_TAG_BITS]),
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.validate(cache_line_addr_validate[i]),
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.invalidate(cache_line_addr_invalidate[i]),
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.cache_hit(cache_line_hit[i]),
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.adr_valid(cache_line_addr_valid[i]),
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.cached_adr_o(cache_line_addr[i]),
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.clk(wb_clk),
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.rst(wb_rst));
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end
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endgenerate
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|
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wire start_writeback, start_fill;
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|
|
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xilinx_ddr2_wb_if_cache_control xilinx_ddr2_wb_if_cache_control0
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|
(
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// Outputs
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.start_writeback (start_writeback),
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.start_fill (start_fill),
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.cache_line_validate (cache_line_addr_validate),
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.cache_line_invalidate (cache_line_addr_invalidate),
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.selected_cache_line (selected_cache_line),
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.selected_cache_line_enc (selected_cache_line_enc),
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// Inputs
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.cache_line_addr_valid (cache_line_addr_valid),
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.cache_line_addr_hit (cache_line_hit),
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.wb_req (wb_req),
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.cache_write (cache_write),
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.writeback_done (do_writeback_finished),
|
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.fill_done (do_readfrom_finished),
|
|
.wb_clk (wb_clk),
|
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.wb_rst (wb_rst));
|
|
|
|
defparam xilinx_ddr2_wb_if_cache_control0.num_lines = `DDR2_CACHE_NUM_LINES;
|
|
defparam xilinx_ddr2_wb_if_cache_control0.num_lines_log2 = `DDR2_CACHE_NUM_LINES_ENC_WIDTH;
|
|
|
|
assign cached_addr = selected_cache_line[0] ? cache_line_addr[0] :
|
|
selected_cache_line[1] ? cache_line_addr[1] :
|
|
selected_cache_line[2] ? cache_line_addr[2] :
|
|
selected_cache_line[3] ? cache_line_addr[3] : 0;
|
|
|
|
assign cache_write = wb_req & wb_we_i & wb_ack_o;
|
|
|
|
assign cache_hit = |(selected_cache_line & cache_line_hit);
|
|
|
|
assign cached_addr_valid = |(selected_cache_line & cache_line_addr_valid);
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|
|
|
assign wb_req_addr_hit = (wb_req & cache_hit & cached_addr_valid);
|
|
|
// Wishbone request detection
|
// Wishbone request detection
|
assign wb_req = wb_stb_i & wb_cyc_i & phy_init_done;
|
assign wb_req = wb_stb_i & wb_cyc_i & phy_init_done;
|
|
|
always @(posedge wb_clk)
|
always @(posedge wb_clk)
|
| Line 212... |
Line 318... |
assign wb_req_new = wb_req & !wb_req_r;
|
assign wb_req_new = wb_req & !wb_req_r;
|
|
|
always @(posedge wb_clk)
|
always @(posedge wb_clk)
|
wb_req_new_r <= wb_req_new;
|
wb_req_new_r <= wb_req_new;
|
|
|
// Register whether it's a hit or not
|
|
// As more lines are added, add them to this check.
|
|
always @(posedge wb_clk)
|
always @(posedge wb_clk)
|
if (wb_rst)
|
if (wb_rst)
|
wb_req_addr_hit <= 0;
|
wb_bursting <= 0;
|
else
|
// Reset if acking end of transfer
|
wb_req_addr_hit <= wb_req & cache_hit & cached_addr_valid;
|
else if (wb_ack_o && wb_cti_i == 3'b111)
|
|
wb_bursting <= 0;
|
|
// Set if beginning new transaction and incrementing burst indicated
|
|
// TODO - double check if this burst is going to go over a cache line
|
|
// boundary - if so don't allow burst, fall back to classic cycles.
|
|
else if (wb_req_new)
|
|
wb_bursting <= (wb_cti_i == 3'b010);
|
|
|
|
// Help constrain additions to appropriate bit-width for wrapping
|
|
assign wb_burst_addr_4beat = wb_adr_i[3:2] + 1;
|
|
assign wb_burst_addr_8beat = wb_adr_i[4:2] + 1;
|
|
|
|
// Increment burst address whenever we get a hit when reading, or
|
|
// when acking and writing.
|
|
assign wb_burst_addr_incr = (wb_req_addr_hit & (!wb_we_i |
|
|
(wb_we_i & wb_ack_o)));
|
|
|
|
// Calculate burst address depending on burst type indicator
|
always @(posedge wb_clk)
|
always @(posedge wb_clk)
|
if (wb_rst)
|
if (wb_rst)
|
wb_ack_o <= 0;
|
wb_burst_addr <= 0;
|
else
|
else if (wb_req_new)
|
wb_ack_o <= wb_req_addr_hit & !wb_ack_o & !wb_ack_o_r;
|
// When we have a bursting read to an address which is in cache then
|
|
// initialise the address to the next word in the burst sequence.
|
|
// If it's a miss, or it's a write, then we just take what's on the
|
|
// bus.
|
|
wb_burst_addr <= !(wb_req_addr_hit & !wb_we_i) ? wb_adr_i[5:2] :
|
|
wb_bte_i==2'b01 ? {wb_adr_i[5:4], wb_burst_addr_4beat }:
|
|
wb_bte_i==2'b10 ? {wb_adr_i[5], wb_burst_addr_8beat }:
|
|
wb_bte_i==2'b11 ? wb_adr_i[5:2] + 1 :
|
|
wb_adr_i[5:2];
|
|
else if (wb_burst_addr_incr & wb_bte_i==2'b01)
|
|
wb_burst_addr[1:0] <= wb_burst_addr[1:0] + 1;
|
|
else if (wb_burst_addr_incr & wb_bte_i==2'b10)
|
|
wb_burst_addr[2:0] <= wb_burst_addr[2:0] + 1;
|
|
else if (wb_burst_addr_incr & wb_bte_i==2'b11)
|
|
wb_burst_addr[3:0] <= wb_burst_addr[3:0] + 1;
|
|
|
|
`ifdef ERR_COUNTER
|
|
reg [26:0] ack_err_cntr;
|
|
|
always @(posedge wb_clk)
|
always @(posedge wb_clk)
|
wb_ack_o_r <= wb_ack_o;
|
if (wb_rst)
|
|
ack_err_cntr <= 0;
|
|
else if (!wb_req)
|
|
ack_err_cntr <= 0;
|
|
else if (|ack_err_cntr)
|
|
ack_err_cntr <= ack_err_cntr + 1;
|
|
else if (wb_req_new & !(|ack_err_cntr))
|
|
ack_err_cntr <= 1;
|
|
|
|
assign ack_err = (&ack_err_cntr);
|
|
|
|
always @(posedge wb_clk)
|
|
ack_err_r <= ack_err;
|
|
|
|
assign wb_err_o = ack_err_r;
|
|
|
|
`else // !`ifdef ERR_COUNTER
|
|
|
|
assign ack_err = 0;
|
|
always @(posedge wb_clk)
|
|
ack_err_r <= 0;
|
|
|
|
assign wb_err_o = 0;
|
|
|
|
`endif
|
|
|
// Address valid logic
|
|
always @(posedge wb_clk)
|
always @(posedge wb_clk)
|
if (wb_rst)
|
if (wb_rst)
|
cached_addr_valid <= 0;
|
wb_ack_o <= 0;
|
else if (do_readfrom_finished)
|
else
|
cached_addr_valid <= 1;
|
wb_ack_o <= wb_req_addr_hit &
|
else if ( do_writeback_finished ) // Data written back, cache not valid
|
(
|
cached_addr_valid <= 0;
|
// Simple acks on classic cycles
|
else if (wb_req & !cache_hit & cached_addr_valid & !cache_dirty)
|
(!wb_bursting && !wb_ack_o && !wb_ack_o_r)
|
// Invalidate cache so a readfrom begins
|
// De-assert ack when we see the final transaction
|
cached_addr_valid <= 0;
|
|| (wb_bursting && !(wb_cti_i==3'b111))
|
|
);
|
|
|
// Address cacheing
|
always @(posedge wb_clk)
|
|
wb_ack_o_r <= wb_ack_o;
|
|
|
|
// Writeback/readfrom lower address generation
|
always @(posedge wb_clk)
|
always @(posedge wb_clk)
|
if (wb_rst)
|
if (wb_rst)
|
cached_addr <= 0;
|
addr_counter <= 0;
|
else if (do_readfrom_start)
|
else if (app_af_wren)
|
cached_addr <= wb_adr_i[31:6];
|
addr_counter <= addr_counter+1;
|
|
|
// Cache dirty signal
|
// Determine if we're writing access requests into DDR2 interface AF
|
always @(posedge wb_clk)
|
always @(posedge wb_clk)
|
if (wb_rst)
|
if (wb_rst)
|
cache_dirty <= 0;
|
do_af_write <= 0;
|
else if (wb_req & wb_we_i & wb_req_addr_hit & wb_ack_o)
|
else if (do_readfrom_start | do_writeback_data_finished)
|
cache_dirty <= 1;
|
do_af_write <= 1;
|
else if (!cached_addr_valid & cache_dirty)
|
else if ((&addr_counter)) // Stop when counter rolls over
|
cache_dirty <= 0;
|
do_af_write <= 0;
|
|
|
|
// Wishbone side of cache enable. Always enabled unless doing DDR2-side
|
|
// things (fill or writeback).
|
|
assign wb_cache_en = !(do_readfrom | do_writeback);
|
|
|
// Wishbone side of cache enable. Important!
|
|
// 1. Enable on first access, if it's not a write
|
|
// 2. Enable if we've just refreshed the cache
|
|
// 3. Enable on ACK'ing for a write
|
|
assign wb_cache_en = (wb_req_new & !wb_we_i) | do_readfrom_finished |
|
|
(wb_req_addr_hit & wb_stb_i & !wb_we_i & !wb_ack_o) |
|
|
(wb_ack_o & wb_we_i);
|
|
|
|
// Writeback detect logic
|
// Writeback detect logic
|
always @(posedge wb_clk)
|
always @(posedge wb_clk)
|
if (wb_rst)
|
if (wb_rst)
|
do_writeback <= 0;
|
do_writeback <= 0;
|
else if (ddr2_write_done) // DDR2 domain signal
|
else if (ddr2_write_done) // DDR2 domain signal
|
do_writeback <= 0;
|
do_writeback <= 0;
|
else if (wb_req & !cache_hit & cached_addr_valid & !doing_writeback & cache_dirty)
|
else if (start_writeback)
|
do_writeback <= 1;
|
do_writeback <= 1;
|
|
|
|
|
always @(posedge wb_clk)
|
always @(posedge wb_clk)
|
do_writeback_r <= do_writeback;
|
do_writeback_r <= do_writeback;
|
|
|
|
// Detect falling edge of do_writeback
|
|
assign do_writeback_data_finished = !do_writeback & do_writeback_r;
|
|
|
|
always @(posedge wb_clk)
|
|
if (wb_rst)
|
|
do_writeback_addresses <= 0;
|
|
else if (do_writeback_data_finished)
|
|
do_writeback_addresses <= 1;
|
|
else if ((&addr_counter))
|
|
do_writeback_addresses <= 0;
|
|
|
|
always @(posedge wb_clk)
|
|
do_writeback_addresses_r <= do_writeback_addresses;
|
|
|
|
// Detect rising edge of do_writeback
|
assign do_writeback_start = do_writeback & !do_writeback_r;
|
assign do_writeback_start = do_writeback & !do_writeback_r;
|
assign do_writeback_finished = !do_writeback & do_writeback_r;
|
// Detect falling edge of address writing control signal
|
assign doing_writeback = do_writeback | do_writeback_r;
|
assign do_writeback_finished = !do_writeback_addresses &
|
|
do_writeback_addresses_r;
|
|
|
// DDR2 Read detect logic
|
// DDR2 Read detect logic
|
always @(posedge wb_clk)
|
always @(posedge wb_clk)
|
if (wb_rst)
|
if (wb_rst)
|
do_readfrom <= 0;
|
do_readfrom <= 0;
|
else if (ddr2_read_done) // DDR2 domain signal
|
else if (ddr2_read_done) // DDR2 domain signal
|
do_readfrom <= 0;
|
do_readfrom <= 0;
|
else if (wb_req & !cache_hit & !cached_addr_valid & !doing_readfrom & !cache_dirty)
|
else if (start_fill)
|
do_readfrom <= 1;
|
do_readfrom <= 1;
|
|
|
always @(posedge wb_clk)
|
always @(posedge wb_clk)
|
do_readfrom_r <= do_readfrom;
|
do_readfrom_r <= do_readfrom;
|
|
|
|
// Detect line fill request rising edge
|
assign do_readfrom_start = do_readfrom & !do_readfrom_r;
|
assign do_readfrom_start = do_readfrom & !do_readfrom_r;
|
|
// Detect line fill request falling edge
|
assign do_readfrom_finished = !do_readfrom & do_readfrom_r;
|
assign do_readfrom_finished = !do_readfrom & do_readfrom_r;
|
assign doing_readfrom = do_readfrom | do_readfrom_r;
|
assign doing_readfrom = do_readfrom | do_readfrom_r;
|
|
|
// Address fifo signals
|
// Address fifo signals
|
assign app_af_wren = (do_writeback_finished | do_readfrom_start);
|
assign app_af_wren = (do_readfrom_r | do_writeback_addresses_r) &
|
assign app_af_cmd[0] = do_readfrom_start; // 1 - read, 0 - write
|
!app_af_afull & do_af_write ;
|
|
assign app_af_cmd[0] = do_readfrom; // 1 - read, 0 - write
|
assign app_af_cmd[2:1] = 0;
|
assign app_af_cmd[2:1] = 0;
|
assign app_af_addr = do_readfrom_start ? {2'd0, wb_adr_i[31:6],3'd0} :
|
|
{2'd0,cached_addr,3'd0};
|
|
|
|
|
assign writeback_af_addr = {1'd0, cached_addr, addr_counter, 3'd0};
|
|
|
|
assign readfrom_af_addr = {1'd0, wb_adr_i[`DDR2_CACHE_TAG_BITS],
|
|
addr_counter, 3'd0};
|
|
|
|
assign app_af_addr = doing_readfrom ? readfrom_af_addr : writeback_af_addr;
|
assign app_wdf_wren = do_writeback_ddr2_fifo_we;
|
assign app_wdf_wren = do_writeback_ddr2_fifo_we;
|
assign app_wdf_data = ddr2_cache_data_o;
|
assign app_wdf_data = ddr2_cache_data_o;
|
assign app_wdf_mask_data = 0;
|
assign app_wdf_mask_data = 0;
|
|
|
always @(posedge wb_clk) if (wb_rst) wb_clk_r <= 0; else wb_clk_r <= ~wb_clk_r;
|
always @(posedge wb_clk)
|
|
if (wb_rst) wb_clk_r <= 0; else wb_clk_r <= ~wb_clk_r;
|
always @(posedge ddr2_clk) wb_clk_in_ddr2_clk <= wb_clk_r;
|
always @(posedge ddr2_clk) wb_clk_in_ddr2_clk <= wb_clk_r;
|
always @(posedge ddr2_clk) wb_clk_in_ddr2_clk_r <= wb_clk_in_ddr2_clk;
|
always @(posedge ddr2_clk) wb_clk_in_ddr2_clk_r <= wb_clk_in_ddr2_clk;
|
|
|
assign wb_clk_edge = wb_clk_in_ddr2_clk & !wb_clk_in_ddr2_clk_r;
|
assign wb_clk_edge = wb_clk_in_ddr2_clk & !wb_clk_in_ddr2_clk_r;
|
|
|
| Line 324... |
Line 508... |
ddr2_clk_phase <= 0;
|
ddr2_clk_phase <= 0;
|
else
|
else
|
ddr2_clk_phase <= ddr2_clk_phase + 1;
|
ddr2_clk_phase <= ddr2_clk_phase + 1;
|
|
|
always @(posedge ddr2_clk)
|
always @(posedge ddr2_clk)
|
do_writeback_ddr2_fifo_we <= (do_writeback_ddr2_shifter_r[0]) |
|
if (ddr2_rst)
|
(do_writeback_ddr2_shifter_r[2]) |
|
do_writeback_ddr2 <= 0;
|
(do_writeback_ddr2_shifter_r[4]) |
|
else if (&ddr2_cache_line_word_addr)
|
(do_writeback_ddr2_shifter_r[6]);
|
do_writeback_ddr2 <= 0;
|
|
else if (!(|ddr2_clk_phase) & do_writeback & // sample WB domain
|
|
!ddr2_write_done)
|
|
do_writeback_ddr2 <= 1;
|
|
|
// Kick off counting when we see that the wb_clk domain is
|
|
// doing a writeback.
|
|
always @(posedge ddr2_clk)
|
always @(posedge ddr2_clk)
|
if (ddr2_rst)
|
if (ddr2_rst)
|
do_writeback_ddr2_shifter <= 4'h0;
|
ddr2_cache_line_word_addr <= 0;
|
else if (|do_writeback_ddr2_shifter)
|
else if (rd_data_valid | (do_writeback_ddr2 & !app_wdf_afull))
|
do_writeback_ddr2_shifter <= {do_writeback_ddr2_shifter[6:0], 1'b0};
|
ddr2_cache_line_word_addr <= ddr2_cache_line_word_addr + 1;
|
else if (!(|ddr2_clk_phase) & do_writeback & !ddr2_write_done) // sample WB domain
|
else if (ddr2_write_done | ddr2_read_done)
|
do_writeback_ddr2_shifter <= 1;
|
ddr2_cache_line_word_addr <= 0;
|
|
|
|
|
|
|
always @(posedge ddr2_clk)
|
always @(posedge ddr2_clk)
|
do_writeback_ddr2_shifter_r <= do_writeback_ddr2_shifter;
|
do_writeback_ddr2_fifo_we <= (do_writeback_ddr2 & !app_wdf_afull);
|
|
|
always @(posedge ddr2_clk)
|
always @(posedge ddr2_clk)
|
if (ddr2_rst)
|
if (ddr2_rst)
|
ddr2_write_done <= 0;
|
ddr2_write_done <= 0;
|
else if (do_writeback_ddr2_shifter[7])
|
else if ((&ddr2_cache_line_word_addr))
|
ddr2_write_done <= 1;
|
ddr2_write_done <= 1;
|
else if ((!(|ddr2_clk_phase)) & !do_writeback) // sample WB domain
|
else if ((!(|ddr2_clk_phase)) & !do_writeback) // sample WB domain
|
ddr2_write_done <= 0;
|
ddr2_write_done <= 0;
|
|
|
always @(posedge ddr2_clk)
|
always @(posedge ddr2_clk)
|
if (ddr2_rst)
|
|
ddr2_cache_addr <= 0;
|
|
else if (rd_data_valid | do_writeback_ddr2_fifo_we)
|
|
ddr2_cache_addr <= ddr2_cache_addr + 1;
|
|
|
|
always @(posedge ddr2_clk)
|
|
rd_data_valid_r <= rd_data_valid;
|
rd_data_valid_r <= rd_data_valid;
|
|
|
// Read done signaling to WB domain
|
// Read done signaling to WB domain
|
always @(posedge ddr2_clk)
|
always @(posedge ddr2_clk)
|
if (ddr2_rst)
|
if (ddr2_rst)
|
ddr2_read_done <= 0;
|
ddr2_read_done <= 0;
|
// Detect read data valid falling edge
|
else if (rd_data_valid_r & (&ddr2_cache_line_word_addr))
|
else if (!rd_data_valid & rd_data_valid_r)
|
|
ddr2_read_done <= 1;
|
ddr2_read_done <= 1;
|
else if (!(|ddr2_clk_phase) & !do_readfrom) // Read WB domain
|
else if (!(|ddr2_clk_phase) & !do_readfrom) // Read WB domain
|
ddr2_read_done <= 0;
|
ddr2_read_done <= 0;
|
|
|
wire [3:0] wb_cache_adr;
|
// Lower word address uses potentially bursting address counter
|
assign wb_cache_adr = wb_adr_i[5:2];
|
assign wb_cache_adr = wb_bursting ?
|
wire [3:0] wb_cache_sel_we;
|
{wb_adr_i[(`DDR2_CACHE_ADDR_WIDTH_WORDS_PER_LINE+2)-1:6],wb_burst_addr}:
|
assign wb_cache_sel_we = {4{wb_we_i}} & wb_sel_i;
|
wb_adr_i[(`DDR2_CACHE_ADDR_WIDTH_WORDS_PER_LINE+2)-1:2];
|
wire ddr2_cache_en;
|
|
wire [15:0] ddr2_cache_we;
|
assign wb_cache_sel_we = {4{wb_we_i & wb_ack_o}} & wb_sel_i;
|
assign ddr2_cache_en = rd_data_valid | (|do_writeback_ddr2_shifter);
|
assign ddr2_cache_en = (rd_data_valid |do_writeback_ddr2);
|
assign ddr2_cache_we = {16{rd_data_valid}};
|
assign ddr2_cache_we = {16{rd_data_valid}};
|
|
|
|
always @(posedge ddr2_clk)
|
|
if (!(|ddr2_clk_phase)) // Read WB domain
|
|
selected_cache_line_enc_ddr2_clk <= selected_cache_line_enc;
|
|
|
// Xilinx Coregen true dual-port RAMB array.
|
|
|
|
|
// Xilinx Coregen true dual-port RAMB
|
// Wishbone side : 32-bit
|
// Wishbone side : 32-bit
|
// DDR2 side : 128-bit
|
// DDR2 side : 128-bit
|
xilinx_ddr2_if_cache cache_mem0
|
xilinx_ddr2_if_cache cache_mem0
|
(
|
(
|
// Wishbone side
|
// Wishbone side
|
.clka(wb_clk),
|
.clka(wb_clk),
|
.ena(wb_cache_en),
|
.ena(wb_cache_en),
|
.wea(wb_cache_sel_we),
|
.wea(wb_cache_sel_we),
|
.addra({8'd0,wb_cache_adr}),
|
.addra({2'd0, selected_cache_line_enc,wb_cache_adr}),
|
.dina(wb_dat_i),
|
.dina(wb_dat_i),
|
.douta(wb_dat_o),
|
.douta(wb_dat_o),
|
|
|
// DDR2 controller side
|
// DDR2 controller side
|
.clkb(ddr2_clk),
|
.clkb(ddr2_clk),
|
.enb(ddr2_cache_en),
|
.enb(ddr2_cache_en),
|
.web(ddr2_cache_we),
|
.web(ddr2_cache_we),
|
.addrb({8'd0,ddr2_cache_addr}),
|
.addrb({2'd0, selected_cache_line_enc_ddr2_clk,
|
|
ddr2_cache_line_word_addr}),
|
.dinb(rd_data_fifo_out),
|
.dinb(rd_data_fifo_out),
|
.doutb(ddr2_cache_data_o));
|
.doutb(ddr2_cache_data_o));
|
|
|
ddr2_mig #
|
ddr2_mig #
|
(
|
(
|
| Line 448... |
Line 630... |
)
|
)
|
ddr2_mig0
|
ddr2_mig0
|
(
|
(
|
.sys_clk (ddr2_if_clk),
|
.sys_clk (ddr2_if_clk),
|
.idly_clk_200 (idly_clk_200),
|
.idly_clk_200 (idly_clk_200),
|
.sys_rst_n (ddr2_if_rst), // Act. high, sync. to ddr2_if_clk
|
.sys_rst_n (ddr2_if_rst),
|
.ddr2_ras_n (ddr2_ras_n),
|
.ddr2_ras_n (ddr2_ras_n),
|
.ddr2_cas_n (ddr2_cas_n),
|
.ddr2_cas_n (ddr2_cas_n),
|
.ddr2_we_n (ddr2_we_n),
|
.ddr2_we_n (ddr2_we_n),
|
.ddr2_cs_n (ddr2_cs_n),
|
.ddr2_cs_n (ddr2_cs_n),
|
.ddr2_cke (ddr2_cke),
|
.ddr2_cke (ddr2_cke),
|
| Line 481... |
Line 663... |
.app_wdf_mask_data (app_wdf_mask_data),
|
.app_wdf_mask_data (app_wdf_mask_data),
|
.phy_init_done (phy_init_done)
|
.phy_init_done (phy_init_done)
|
);
|
);
|
|
|
|
|
endmodule // ml501_ddr2_if
|
endmodule // xilinx_ddr2_if2
|
|
|
// Local Variables:
|
// Local Variables:
|
// verilog-library-directories:("." "ddr2_mig")
|
// verilog-library-directories:("." "ddr2_mig")
|
// verilog-library-extensions:(".v" ".h")
|
// verilog-library-extensions:(".v" ".h")
|
// End:
|
// End:
|
|
|
No newline at end of file
|
No newline at end of file
|
|
|
|
module xilinx_ddr2_wb_if_cache_adr_reg
|
|
(adr_i, validate, invalidate,
|
|
cached_adr_o, cache_hit, adr_valid,
|
|
clk, rst);
|
|
|
|
parameter full_adr_width = 32;
|
|
parameter word_adr_width = 2; // 4 bytes per word
|
|
parameter line_adr_width = 8; // 256 words per "line"
|
|
|
|
parameter tag_width = full_adr_width - line_adr_width - word_adr_width;
|
|
|
|
|
|
input [full_adr_width-1: word_adr_width + line_adr_width] adr_i;
|
|
input validate;
|
|
input invalidate;
|
|
output [full_adr_width-1: word_adr_width + line_adr_width] cached_adr_o;
|
|
output cache_hit;
|
|
output reg adr_valid;
|
|
|
|
input clk, rst;
|
|
|
|
reg [tag_width-1:0] cached_adr;
|
|
|
|
assign cached_adr_o = cached_adr;
|
|
|
|
always @(posedge clk)
|
|
if (rst)
|
|
cached_adr <= 0;
|
|
else if (validate)
|
|
cached_adr <= adr_i;
|
|
|
|
always @(posedge clk)
|
|
if (rst)
|
|
adr_valid <= 0;
|
|
else if (validate)
|
|
adr_valid <= 1;
|
|
else if (invalidate)
|
|
adr_valid <= 0;
|
|
|
|
assign cache_hit = (adr_i == cached_adr);
|
|
|
|
endmodule // xilinx_ddr2_wb_if_cache_adr_reg
|
|
|
|
module xilinx_ddr2_wb_if_cache_control
|
|
( cache_line_addr_valid, cache_line_addr_hit,
|
|
wb_req,
|
|
cache_write,
|
|
writeback_done, fill_done,
|
|
start_writeback, start_fill,
|
|
cache_line_validate, cache_line_invalidate,
|
|
selected_cache_line, selected_cache_line_enc,
|
|
wb_clk, wb_rst);
|
|
|
|
parameter num_lines = 16;
|
|
parameter num_lines_log2 = 4;
|
|
|
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input [num_lines-1:0] cache_line_addr_valid;
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input [num_lines-1:0] cache_line_addr_hit;
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input wb_req;
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input cache_write;
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input writeback_done, fill_done;
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output reg start_writeback;
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output reg start_fill;
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output reg [num_lines-1:0] cache_line_validate;
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output reg [num_lines-1:0] cache_line_invalidate;
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output [num_lines-1:0] selected_cache_line;
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output reg [num_lines_log2-1:0] selected_cache_line_enc;
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input wb_clk, wb_rst;
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reg [num_lines-1:0] dirty;
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reg [num_lines-1:0] selected_cache_line_from_miss;
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reg selected_cache_line_new;
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reg invalidate_clean_line;
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reg [num_lines-1:0] selected_cache_line_r;
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reg [num_lines-1:0] selected_cache_line_r2;
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reg wb_req_r;
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wire wb_req_new;
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reg wb_req_new_r;
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always @(posedge wb_clk)
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wb_req_r <= wb_req;
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assign wb_req_new = wb_req & !wb_req_r;
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always @(posedge wb_clk)
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wb_req_new_r <= wb_req_new;
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// Select a cache line when we miss. Currently very simply is round robin
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always @(posedge wb_clk)
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if (wb_rst)
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selected_cache_line_from_miss <= 1;
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else if (wb_req_new_r & !(|selected_cache_line_r)) // miss,no line selected
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// Shift select bit one
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selected_cache_line_from_miss
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<= {selected_cache_line_from_miss[num_lines-2:0],
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selected_cache_line_from_miss[num_lines-1]};
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// Line selection logic, when line address is valid and hit, we select
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always @(posedge wb_clk)
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if (wb_rst)
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selected_cache_line_r <= 0;
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else if (wb_req_new)
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selected_cache_line_r <= cache_line_addr_valid & cache_line_addr_hit;
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else if (wb_req_new_r & !(|selected_cache_line_r))
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selected_cache_line_r <= selected_cache_line_from_miss;
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always @(posedge wb_clk)
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selected_cache_line_r2 <= selected_cache_line_r;
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assign selected_cache_line = selected_cache_line_r2;
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// A new line of cache has been selected
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always @(posedge wb_clk)
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if (wb_rst)
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selected_cache_line_new <= 0;
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else if (wb_req_new & (&(cache_line_addr_valid & cache_line_addr_hit)))
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// New line address selected
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selected_cache_line_new <= 1;
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else if ((!selected_cache_line_new) & wb_req_new_r)
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// Didn't select one last time, so we must have forced ourselves to
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// select a new one
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selected_cache_line_new <= 1;
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else if (selected_cache_line_new)
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selected_cache_line_new <= 0;
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always @(posedge wb_clk)
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if (wb_rst)
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dirty <= 0;
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else if (cache_write)
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dirty <= dirty | selected_cache_line_r;
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else if (writeback_done)
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dirty <= dirty & ~(selected_cache_line_r);
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// Validate the cache line address in the register when line filled
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always @(posedge wb_clk)
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if (wb_rst)
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cache_line_validate <= 0;
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else if (fill_done)
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cache_line_validate <= selected_cache_line_r;
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else if (|cache_line_validate)
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cache_line_validate <= 0;
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// Invalidate the cache line address in the register when line written back
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always @(posedge wb_clk)
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if (wb_rst)
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cache_line_invalidate <= 0;
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else if (writeback_done | invalidate_clean_line)
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cache_line_invalidate <= selected_cache_line_r;
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else if (|cache_line_invalidate)
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cache_line_invalidate <= 0;
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// Initiate-writeback logic
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always @(posedge wb_clk)
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if (wb_rst)
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start_writeback <= 0;
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else if (selected_cache_line_new & (|(dirty & selected_cache_line_r)) &
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(|(selected_cache_line_r & cache_line_addr_valid)) &
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!(|(cache_line_addr_hit & selected_cache_line_r)))
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start_writeback <= 1;
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else if (start_writeback)
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start_writeback <= 0;
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// Invalidate lines which we haven't written to so we can fill them
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always @(posedge wb_clk)
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if (wb_rst)
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invalidate_clean_line <= 0;
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else if (invalidate_clean_line)
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invalidate_clean_line <= 0;
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else if ((selected_cache_line_new) & // New line selected
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!(|(dirty & selected_cache_line_r)) & // It's not dirty
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// It's valid, but we've selected it so we're trashing it
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(|(selected_cache_line_r & cache_line_addr_valid)) &
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!(|(cache_line_addr_hit & selected_cache_line_r))) // Not a hit
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invalidate_clean_line <= 1;
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reg invalidate_clean_line_r;
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always @(posedge wb_clk)
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invalidate_clean_line_r <= invalidate_clean_line;
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// Initiate-fill logic
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always @(posedge wb_clk)
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if (wb_rst)
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start_fill <= 0;
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else if (((selected_cache_line_new) & // New line selected
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// not valid
|
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!(|(cache_line_addr_valid & selected_cache_line_r))) |
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writeback_done | invalidate_clean_line_r
|
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)
|
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start_fill <= 1;
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else if (start_fill)
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start_fill <= 0;
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// Relies on there only being 4 lines
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always @(posedge wb_clk)
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if (selected_cache_line_r[0])
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selected_cache_line_enc <= 0;
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else if (selected_cache_line_r[1])
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selected_cache_line_enc <= 1;
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else if (selected_cache_line_r[2])
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selected_cache_line_enc <= 2;
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else if (selected_cache_line_r[3])
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selected_cache_line_enc <= 3;
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endmodule // xilinx_ddr2_wb_if_cache_control
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No newline at end of file
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