OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [xilinx_ddr2/] [xilinx_ddr2_if.v] - Diff between revs 412 and 439

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 412 Rev 439
Line 102... Line 102...
 */
 */
module xilinx_ddr2_if (
module xilinx_ddr2_if (
    input [31:0]       wb_adr_i,
    input [31:0]       wb_adr_i,
    input              wb_stb_i,
    input              wb_stb_i,
    input              wb_cyc_i,
    input              wb_cyc_i,
 
    input [2:0]        wb_cti_i,
 
    input [1:0]        wb_bte_i,
    input              wb_we_i,
    input              wb_we_i,
    input [3:0]        wb_sel_i,
    input [3:0]        wb_sel_i,
    input [31:0]       wb_dat_i,
    input [31:0]       wb_dat_i,
    output [31:0]      wb_dat_o,
    output [31:0]      wb_dat_o,
    output reg         wb_ack_o,
    output reg         wb_ack_o,
Line 197... Line 199...
   wire [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data;
   wire [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data;
   wire                         rd_data_valid;
   wire                         rd_data_valid;
   wire [(APPDATA_WIDTH)-1:0]    rd_data_fifo_out;
   wire [(APPDATA_WIDTH)-1:0]    rd_data_fifo_out;
   wire                         phy_init_done;
   wire                         phy_init_done;
 
 
 
 
   assign cache_hit = (cached_addr ==  wb_adr_i[31:6]) & cached_addr_valid;
   assign cache_hit = (cached_addr ==  wb_adr_i[31:6]) & cached_addr_valid;
 
 
   // Wishbone request detection
   // Wishbone request detection
   assign wb_req = wb_stb_i & wb_cyc_i & phy_init_done;
   assign wb_req = wb_stb_i & wb_cyc_i & phy_init_done;
 
 
Line 364... Line 365...
 
 
   // Read done signaling to WB domain
   // Read done signaling to WB domain
   always @(posedge ddr2_clk)
   always @(posedge ddr2_clk)
     if (ddr2_rst)
     if (ddr2_rst)
       ddr2_read_done <= 0;
       ddr2_read_done <= 0;
     else if (!rd_data_valid & rd_data_valid_r) // Detect read data valid falling edge
   // Detect read data valid falling edge
 
     else if (!rd_data_valid & rd_data_valid_r)
       ddr2_read_done <= 1;
       ddr2_read_done <= 1;
     else if (!(|ddr2_clk_phase) & !do_readfrom) // Read WB domain
     else if (!(|ddr2_clk_phase) & !do_readfrom) // Read WB domain
       ddr2_read_done <= 0;
       ddr2_read_done <= 0;
 
 
   wire [3:0]                    wb_cache_adr;
   wire [3:0]                    wb_cache_adr;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.