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######################################################################
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######################################################################
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#### ####
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#### ####
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#### ORPSoCv2 Testbenches Makefile ####
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#### ORPSoCv2 Xilinx simulation Makefile ####
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#### ####
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#### ####
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#### Description ####
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#### Description ####
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#### ORPSoCv2 Testbenches Makefile, containing rules for ####
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#### ORPSoCv2 Testbenches Makefile, containing rules for ####
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#### configuring and running different tests on the current ####
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#### configuring and running different tests on the current ####
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#### ORPSoC(v2) design. ####
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#### ORPSoC(v2) design. ####
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print-tests:
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print-tests:
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@echo; echo; echo "\t### Software tests to be run ###"; echo;
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@echo; echo; echo "\t### Software tests to be run ###"; echo;
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@echo $(TESTS)
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@echo $(TESTS)
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@echo
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@echo
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# Backend tool path
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# Check that the XILINX_PATH variable is set
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ifeq ($(XILINX_PATH),)
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$(error XILINX_PATH environment variable not set. Set it and rerun)
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endif
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XILINX_SETTINGS_SCRIPT=$(XILINX_PATH)/settings32.sh
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XILINX_SETTINGS_SCRIPT_EXISTS=$(shell if [ -e $(XILINX_SETTINGS_SCRIPT) ]; then echo 1; else echo 0; fi)
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ifeq ($(XILINX_SETTINGS_SCRIPT_EXISTS),0)
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$(error XILINX_PATH variable not set correctly. Cannot find $$XILINX_PATH/settings32.sh)
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endif
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# Simulation directories
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# Simulation directories
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SIM_DIR ?=$(BOARD_DIR)/sim
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SIM_DIR ?=$(BOARD_DIR)/sim
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RTL_SIM_DIR=$(SIM_DIR)
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RTL_SIM_DIR=$(SIM_DIR)
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RTL_SIM_RUN_DIR=$(RTL_SIM_DIR)/run
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RTL_SIM_RUN_DIR=$(RTL_SIM_DIR)/run
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RTL_SIM_BIN_DIR=$(RTL_SIM_DIR)/bin
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RTL_SIM_BIN_DIR=$(RTL_SIM_DIR)/bin
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# This one is the board build's backend dir.
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# This one is the board build's backend dir.
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BOARD_BACKEND_DIR=$(BOARD_DIR)/backend
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BOARD_BACKEND_DIR=$(BOARD_DIR)/backend
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BOARD_BACKEND_VERILOG_DIR=$(BOARD_BACKEND_DIR)/rtl/verilog
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BOARD_BACKEND_VERILOG_DIR=$(BOARD_BACKEND_DIR)/rtl/verilog
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TECHNOLOGY_BACKEND_DIR=$(BOARD_DIR)/../backend
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TECHNOLOGY_BACKEND_DIR=$(BOARD_DIR)/../backend
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# This path is for the technology library
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# This path is for the technology library
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TECHNOLOGY_BACKEND_VERILOG_DIR=$(TECHNOLOGY_BACKEND_DIR)/rtl/verilog
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#TECHNOLOGY_BACKEND_VERILOG_DIR=$(TECHNOLOGY_BACKEND_DIR)/rtl/verilog
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# Depends on the XILINX_PATH variable - we check above if it's set properly.
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TECHNOLOGY_BACKEND_VERILOG_DIR=$(XILINX_PATH)/verilog
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# Synthesis directory for board
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# Synthesis directory for board
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BOARD_SYN_DIR=$(BOARD_DIR)/syn/synplify
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BOARD_SYN_DIR=$(BOARD_DIR)/syn/synplify
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BOARD_SYN_OUT_DIR=$(BOARD_SYN_DIR)/out
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BOARD_SYN_OUT_DIR=$(BOARD_SYN_DIR)/out
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