URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [sw/] [board/] [include/] [board.h] - Diff between revs 496 and 655

Rev 496	Rev 655
Line 9...	Line 9...
`//`	`//`
`// Uncomment the appropriate bootloader define. This will effect the bootrom.S`	`// Uncomment the appropriate bootloader define. This will effect the bootrom.S`
`// file, which is compiled and converted into Verilog for inclusion at`	`// file, which is compiled and converted into Verilog for inclusion at`
`// synthesis time. See bootloader/bootloader.S for details on each option.`	`// synthesis time. See bootloader/bootloader.S for details on each option.`
`#ifndef PRELOAD_RAM`	`#ifndef PRELOAD_RAM`
`#define BOOTROM_SPI_FLASH`	`//#define BOOTROM_SPI_FLASH`
`//#define BOOTROM_GOTO_RESET`	`#define BOOTROM_GOTO_RESET`
`//#define BOOTROM_LOOP_AT_ZERO`	`//#define BOOTROM_LOOP_AT_ZERO`
`//#define BOOTROM_LOOP_IN_ROM`	`//#define BOOTROM_LOOP_IN_ROM`
`#else`	`#else`
`#define BOOTROM_GOTO_RESET`	`#define BOOTROM_GOTO_RESET`
`#endif`	`#endif`
Line 61...	Line 61...
`//`	`//`
`// OR1200 tick timer period define`	`// OR1200 tick timer period define`
`//`	`//`
`#define TICKS_PER_SEC 100`	`#define TICKS_PER_SEC 100`

	`//`
	`// CFI flash controller base`
	`//`
	`#define CFI_CTRL_BASE 0xf0000000`

`//`	`//`
`// UART driver configuration`	`// UART driver configuration`
`//`	`//`
`#define UART_NUM_CORES 1`	`#define UART_NUM_CORES 1`