URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [sw/] [board/] [include/] [board.h] - Diff between revs 415 and 426

Rev 415	Rev 426
Line 1...	Line 1...
`#ifndef _BOARD_H_`	`#ifndef _BOARD_H_`
`#define _BOARD_H_`	`#define _BOARD_H_`

`#define IN_CLK 50000000 // Hz`	`#define IN_CLK 50000000 // Hz`
`//#define IN_CLK 32000000 // Hz`
`//#define IN_CLK 30000000 // HZ`
`//#define IN_CLK 24000000 // HZ`
`//#define IN_CLK 20000000 // HZ`
`//#define IN_CLK 18000000 // HZ`
`//#define IN_CLK 16000000 // HZ`

`//`	`//`
`// ROM bootloader`	`// ROM bootloader`
`//`	`//`
`// Uncomment the appropriate bootloader define. This will effect the bootrom.S`	`// Uncomment the appropriate bootloader define. This will effect the bootrom.S`
Line 20...	Line 14...
`//#define BOOTROM_GOTO_RESET`	`//#define BOOTROM_GOTO_RESET`
`//#define BOOTROM_LOOP_AT_ZERO`	`//#define BOOTROM_LOOP_AT_ZERO`
`//#define BOOTROM_LOOP_IN_ROM`	`//#define BOOTROM_LOOP_IN_ROM`

`// Address bootloader should start from in FLASH`	`// Address bootloader should start from in FLASH`
	`// Last 256KB of 2MB flash - offset 0x1c0000 (2MB-256KB)`
`#define BOOTROM_ADDR_BYTE2 0x1c`	`#define BOOTROM_ADDR_BYTE2 0x1c`
`#define BOOTROM_ADDR_BYTE1 0x00`	`#define BOOTROM_ADDR_BYTE1 0x00`
`#define BOOTROM_ADDR_BYTE0 0x00`	`#define BOOTROM_ADDR_BYTE0 0x00`
`// Causes SPI bootloader to loop if SPI didn't give correct size of image`	`// Causes SPI bootloader to loop if SPI didn't give correct size of image`
`#define SPI_RETRY_IF_INSANE_SIZEWORD`	`#define SPI_RETRY_IF_INSANE_SIZEWORD`