URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [sw/] [board/] [include/] [board.h] - Diff between revs 468 and 479

Rev 468	Rev 479
Line 7...	Line 7...
`// ROM bootloader`	`// ROM bootloader`
`//`	`//`
`// Uncomment the appropriate bootloader define. This will effect the bootrom.S`	`// Uncomment the appropriate bootloader define. This will effect the bootrom.S`
`// file, which is compiled and converted into Verilog for inclusion at`	`// file, which is compiled and converted into Verilog for inclusion at`
`// synthesis time. See bootloader/bootloader.S for details on each option.`	`// synthesis time. See bootloader/bootloader.S for details on each option.`
	`#ifndef PRELOAD_RAM`
`#define BOOTROM_SPI_FLASH`	`#define BOOTROM_SPI_FLASH`
`//#define BOOTROM_GOTO_RESET`	`//#define BOOTROM_GOTO_RESET`
`//#define BOOTROM_LOOP_AT_ZERO`	`//#define BOOTROM_LOOP_AT_ZERO`
`//#define BOOTROM_LOOP_IN_ROM`	`//#define BOOTROM_LOOP_IN_ROM`
	`#else`
	`#define BOOTROM_GOTO_RESET`
	`#endif`

`// Address bootloader should start from in FLASH`	`// Address bootloader should start from in FLASH`
`// Last 256KB of 2MB flash - offset 0x1c0000 (2MB-256KB)`	`// Last 256KB of 2MB flash - offset 0x1c0000 (2MB-256KB)`
`#define BOOTROM_ADDR_BYTE2 0x1c`	`#define BOOTROM_ADDR_BYTE2 0x1c`
`#define BOOTROM_ADDR_BYTE1 0x00`	`#define BOOTROM_ADDR_BYTE1 0x00`