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Line 196... |
XST_FILE=$(DESIGN_NAME).xst
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XST_FILE=$(DESIGN_NAME).xst
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PRJ_FILE=$(DESIGN_NAME).prj
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PRJ_FILE=$(DESIGN_NAME).prj
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NGC_FILE=$(DESIGN_NAME).ngc
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NGC_FILE=$(DESIGN_NAME).ngc
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NETLIST_FILE=$(DESIGN_NAME).v
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NETLIST_FILE=$(DESIGN_NAME).v
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XST_PRJ_FILE_SRC_DECLARE=verilog work
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XST_PRJ_FILE_SRC_DECLARE=verilog work
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print-config:
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print-config:
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$(Q)echo; echo "\t### Synthesis make configuration ###"; echo
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$(Q)echo; echo "\t### Synthesis make configuration ###"; echo
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$(Q)echo "\tFPGA_PART="$(FPGA_PART)
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$(Q)echo "\tFPGA_PART="$(FPGA_PART)
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Line 281... |
Line 282... |
$(NGC_FILE): $(PRJ_FILE) $(XST_FILE) $(XCF_FILE) $(GENERATED_DEFINES)
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$(NGC_FILE): $(PRJ_FILE) $(XST_FILE) $(XCF_FILE) $(GENERATED_DEFINES)
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$(Q)echo; echo "\t#### Running XST ####"; echo;
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$(Q)echo; echo "\t#### Running XST ####"; echo;
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$(Q)(. $(XILINX_SETTINGS_SCRIPT) ; xst -ifn $(XST_FILE) $(XILINX_FLAGS) $(XST_FLAGS) )
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$(Q)(. $(XILINX_SETTINGS_SCRIPT) ; xst -ifn $(XST_FILE) $(XILINX_FLAGS) $(XST_FLAGS) )
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$(Q)echo
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$(Q)echo
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netlist: $(NETLIST_FILE)
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# Netlist generation command
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# Netlist generation command
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$(NETLIST_FILE): $(NGC_FILE)
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$(NETLIST_FILE): $(NGC_FILE)
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$(Q)echo; echo "\t#### Generating verilog netlist ####"; echo;
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$(Q)echo; echo "\t#### Generating verilog netlist ####"; echo;
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$(Q)(. $(XILINX_SETTINGS_SCRIPT) ; \
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$(Q)(. $(XILINX_SETTINGS_SCRIPT) ; \
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netgen -sim -aka -dir . -ofmt verilog $< -w $@ )
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netgen -sim -aka -dir . -ofmt verilog $< -w $@ )
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