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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [backend/] [par/] [bin/] [Makefile] - Diff between revs 568 and 638

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Rev 568 Rev 638
Line 75... Line 75...
$(NGC_FILE):
$(NGC_FILE):
        $(Q)$(MAKE) -C $(BOARD_SYN_RUN_DIR) $(DESIGN_NAME).ngc
        $(Q)$(MAKE) -C $(BOARD_SYN_RUN_DIR) $(DESIGN_NAME).ngc
 
 
$(NGD_FILE): $(UCF_FILE) $(NGC_FILE)
$(NGD_FILE): $(UCF_FILE) $(NGC_FILE)
        @echo; echo "\t#### Running NGDBuild ####";
        @echo; echo "\t#### Running NGDBuild ####";
        $(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
        $(Q)ngdbuild -p $(FPGA_PART) -sd $(BOARD_BACKEND_BIN_DIR) \
        ngdbuild -p $(FPGA_PART) -sd $(BOARD_BACKEND_BIN_DIR) -uc $(UCF_FILE) \
        -uc $(UCF_FILE) $(NGC_FILE) $@
        $(NGC_FILE) $@ )
 
 
 
#This target uses Xilinx tools to perform Mapping
#This target uses Xilinx tools to perform Mapping
$(MAPPED_NCD): $(NGD_FILE)
$(MAPPED_NCD): $(NGD_FILE)
        @echo; echo "\t#### Mapping ####";
        @echo; echo "\t#### Mapping ####";
        $(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
        $(Q) export XIL_MAP_NO_DSP_AUTOREG=1 && \
        export XIL_MAP_NO_DSP_AUTOREG=1 && \
 
        export XIL_MAP_ALLOW_ANY_DLL_INPUT=1 && \
        export XIL_MAP_ALLOW_ANY_DLL_INPUT=1 && \
        map -p $(FPGA_PART) -detail -pr b -cm ${XILINX_AREA_TARGET} \
        map -p $(FPGA_PART) -detail -pr b -cm ${XILINX_AREA_TARGET} \
        -timing -ol high -w $(XILINX_FLAGS) -o $@ -xe n $(NGD_FILE) $(PCF_FILE))
        -timing -ol high -w $(XILINX_FLAGS) -o $@ -xe n $(NGD_FILE) $(PCF_FILE)
 
 
#This target uses Xilinx tools to Place & Route the design
#This target uses Xilinx tools to Place & Route the design
$(PARRED_NCD): $(MAPPED_NCD)
$(PARRED_NCD): $(MAPPED_NCD)
        @echo; echo "\t#### PAR'ing ####";
        @echo; echo "\t#### PAR'ing ####";
        $(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
        $(Q)par -w -ol high $(XILINX_FLAGS) $< $@ $(PCD_FILE)
        par -w -ol high $(XILINX_FLAGS) $< $@ $(PCD_FILE) )
 
 
 
#This target uses Xilinx tools to generate a bitstream for download
#This target uses Xilinx tools to generate a bitstream for download
$(BIT_FILE): $(PARRED_NCD)
$(BIT_FILE): $(PARRED_NCD)
        @echo; echo "\t#### Generating .bit file ####";
        @echo; echo "\t#### Generating .bit file ####";
        $(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
        $(Q)bitgen -w $(XILINX_FLAGS) -g StartUpClk:JtagClk $< $@
        bitgen -w $(XILINX_FLAGS) -g StartUpClk:JtagClk $< $@ )
 
 
 
$(BIT_FILE_FOR_SPI): $(PARRED_NCD)
$(BIT_FILE_FOR_SPI): $(PARRED_NCD)
        @echo; echo "\t#### Generating .bit file for SPI load ####";
        @echo; echo "\t#### Generating .bit file for SPI load ####";
        $(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
        $(Q)bitgen -w $(XILINX_FLAGS) -g StartUpClk:CClk $< $@
        bitgen -w $(XILINX_FLAGS) -g StartUpClk:CClk $< $@ )
 
 
 
# Generate MCS with bootloader specified by user, if BOOTLOADER_BIN defined.
# Generate MCS with bootloader specified by user, if BOOTLOADER_BIN defined.
ifeq ($(BOOTLOADER_BIN),)
ifeq ($(BOOTLOADER_BIN),)
$(MCS_FILE): $(BIT_FILE_FOR_SPI)
$(MCS_FILE): $(BIT_FILE_FOR_SPI)
        @echo; echo "\t#### Generating .mcs file for SPI load ####";
        @echo; echo "\t#### Generating .mcs file for SPI load ####";
        $(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
        $(Q)promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $<
        promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< )
 
else
else
$(MCS_FILE): $(BIT_FILE_FOR_SPI)
$(MCS_FILE): $(BIT_FILE_FOR_SPI)
        @echo; echo "\t#### Generating .mcs file with bootloader for SPI load ####";
        @echo; echo "\t#### Generating .mcs file with bootloader for SPI load ####";
        $(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
        $(Q)promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< \
        promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< \
        -data_file up $(SPI_BOOTLOADER_SW_OFFSET_HEX) $(BOOTLOADER_BIN)
        -data_file up $(SPI_BOOTLOADER_SW_OFFSET_HEX) $(BOOTLOADER_BIN) \
 
         )
 
endif
endif
 
 
#this target downloads the bitstream to the target fpga
#this target downloads the bitstream to the target fpga
download: $(BIT_FILE) $(BATCH_FILE)
download: $(BIT_FILE) $(BATCH_FILE)
        $(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
        $(Q)impact -batch $(BATCH_FILE)
        impact -batch $(BATCH_FILE) )
 
 
 
#This target uses netgen to make a simulation netlist
#This target uses netgen to make a simulation netlist
netlist: $(PARRED_NCD)
netlist: $(PARRED_NCD)
        @echo; echo "\t#### Generating netlist ####";
        @echo; echo "\t#### Generating netlist ####";
        $(Q)(. $(XILINX_SETTINGS_SCRIPT) && \
        $(Q)netgen -ofmt verilog -sim -dir netlist -pcf $(PCF_FILE) $<
        netgen -ofmt verilog -sim -dir netlist -pcf $(PCF_FILE) $<)
 
 
 
#This one uses TRCE to make a timing report
#This one uses TRCE to make a timing report
timingreport: $(PARRED_NCD)
timingreport: $(PARRED_NCD)
        @echo; echo "\t#### Generating timing report ####";
        @echo; echo "\t#### Generating timing report ####";
        $(Q)(. $(XILINX_SETTINGS_SCRIPT) && \
        $(Q)trce $(TIMING_REPORT_OPTIONS) $<
        trce $(TIMING_REPORT_OPTIONS) $< )
 
 
 
 
 
clean:
clean:
        $(Q)rm -rf *.* xlnx_auto* _xmsgs
        $(Q)rm -rf *.* xlnx_auto* _xmsgs
 
 

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