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Line 75... |
$(NGC_FILE):
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$(NGC_FILE):
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$(Q)$(MAKE) -C $(BOARD_SYN_RUN_DIR) $(DESIGN_NAME).ngc
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$(Q)$(MAKE) -C $(BOARD_SYN_RUN_DIR) $(DESIGN_NAME).ngc
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$(NGD_FILE): $(UCF_FILE) $(NGC_FILE)
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$(NGD_FILE): $(UCF_FILE) $(NGC_FILE)
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@echo; echo "\t#### Running NGDBuild ####";
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@echo; echo "\t#### Running NGDBuild ####";
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$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
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$(Q)ngdbuild -p $(FPGA_PART) -sd $(BOARD_BACKEND_BIN_DIR) \
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ngdbuild -p $(FPGA_PART) -sd $(BOARD_BACKEND_BIN_DIR) -uc $(UCF_FILE) \
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-uc $(UCF_FILE) $(NGC_FILE) $@
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$(NGC_FILE) $@ )
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#This target uses Xilinx tools to perform Mapping
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#This target uses Xilinx tools to perform Mapping
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$(MAPPED_NCD): $(NGD_FILE)
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$(MAPPED_NCD): $(NGD_FILE)
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@echo; echo "\t#### Mapping ####";
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@echo; echo "\t#### Mapping ####";
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$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
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$(Q) export XIL_MAP_NO_DSP_AUTOREG=1 && \
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export XIL_MAP_NO_DSP_AUTOREG=1 && \
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export XIL_MAP_ALLOW_ANY_DLL_INPUT=1 && \
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export XIL_MAP_ALLOW_ANY_DLL_INPUT=1 && \
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map -p $(FPGA_PART) -detail -pr b -cm ${XILINX_AREA_TARGET} \
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map -p $(FPGA_PART) -detail -pr b -cm ${XILINX_AREA_TARGET} \
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-timing -ol high -w $(XILINX_FLAGS) -o $@ -xe n $(NGD_FILE) $(PCF_FILE))
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-timing -ol high -w $(XILINX_FLAGS) -o $@ -xe n $(NGD_FILE) $(PCF_FILE)
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#This target uses Xilinx tools to Place & Route the design
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#This target uses Xilinx tools to Place & Route the design
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$(PARRED_NCD): $(MAPPED_NCD)
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$(PARRED_NCD): $(MAPPED_NCD)
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@echo; echo "\t#### PAR'ing ####";
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@echo; echo "\t#### PAR'ing ####";
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$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
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$(Q)par -w -ol high $(XILINX_FLAGS) $< $@ $(PCD_FILE)
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par -w -ol high $(XILINX_FLAGS) $< $@ $(PCD_FILE) )
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#This target uses Xilinx tools to generate a bitstream for download
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#This target uses Xilinx tools to generate a bitstream for download
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$(BIT_FILE): $(PARRED_NCD)
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$(BIT_FILE): $(PARRED_NCD)
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@echo; echo "\t#### Generating .bit file ####";
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@echo; echo "\t#### Generating .bit file ####";
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$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
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$(Q)bitgen -w $(XILINX_FLAGS) -g StartUpClk:JtagClk $< $@
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bitgen -w $(XILINX_FLAGS) -g StartUpClk:JtagClk $< $@ )
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$(BIT_FILE_FOR_SPI): $(PARRED_NCD)
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$(BIT_FILE_FOR_SPI): $(PARRED_NCD)
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@echo; echo "\t#### Generating .bit file for SPI load ####";
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@echo; echo "\t#### Generating .bit file for SPI load ####";
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$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
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$(Q)bitgen -w $(XILINX_FLAGS) -g StartUpClk:CClk $< $@
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bitgen -w $(XILINX_FLAGS) -g StartUpClk:CClk $< $@ )
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# Generate MCS with bootloader specified by user, if BOOTLOADER_BIN defined.
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# Generate MCS with bootloader specified by user, if BOOTLOADER_BIN defined.
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ifeq ($(BOOTLOADER_BIN),)
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ifeq ($(BOOTLOADER_BIN),)
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$(MCS_FILE): $(BIT_FILE_FOR_SPI)
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$(MCS_FILE): $(BIT_FILE_FOR_SPI)
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@echo; echo "\t#### Generating .mcs file for SPI load ####";
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@echo; echo "\t#### Generating .mcs file for SPI load ####";
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$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
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$(Q)promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $<
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promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< )
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else
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else
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$(MCS_FILE): $(BIT_FILE_FOR_SPI)
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$(MCS_FILE): $(BIT_FILE_FOR_SPI)
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@echo; echo "\t#### Generating .mcs file with bootloader for SPI load ####";
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@echo; echo "\t#### Generating .mcs file with bootloader for SPI load ####";
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$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
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$(Q)promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< \
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promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< \
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-data_file up $(SPI_BOOTLOADER_SW_OFFSET_HEX) $(BOOTLOADER_BIN)
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-data_file up $(SPI_BOOTLOADER_SW_OFFSET_HEX) $(BOOTLOADER_BIN) \
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)
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endif
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endif
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#this target downloads the bitstream to the target fpga
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#this target downloads the bitstream to the target fpga
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download: $(BIT_FILE) $(BATCH_FILE)
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download: $(BIT_FILE) $(BATCH_FILE)
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$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
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$(Q)impact -batch $(BATCH_FILE)
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impact -batch $(BATCH_FILE) )
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#This target uses netgen to make a simulation netlist
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#This target uses netgen to make a simulation netlist
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netlist: $(PARRED_NCD)
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netlist: $(PARRED_NCD)
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@echo; echo "\t#### Generating netlist ####";
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@echo; echo "\t#### Generating netlist ####";
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$(Q)(. $(XILINX_SETTINGS_SCRIPT) && \
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$(Q)netgen -ofmt verilog -sim -dir netlist -pcf $(PCF_FILE) $<
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netgen -ofmt verilog -sim -dir netlist -pcf $(PCF_FILE) $<)
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#This one uses TRCE to make a timing report
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#This one uses TRCE to make a timing report
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timingreport: $(PARRED_NCD)
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timingreport: $(PARRED_NCD)
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@echo; echo "\t#### Generating timing report ####";
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@echo; echo "\t#### Generating timing report ####";
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$(Q)(. $(XILINX_SETTINGS_SCRIPT) && \
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$(Q)trce $(TIMING_REPORT_OPTIONS) $<
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trce $(TIMING_REPORT_OPTIONS) $< )
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clean:
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clean:
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$(Q)rm -rf *.* xlnx_auto* _xmsgs
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$(Q)rm -rf *.* xlnx_auto* _xmsgs
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