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* Getting Started::
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* Getting Started::
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* Reference Design::
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* Reference Design::
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* Board Designs::
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* Board Designs::
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* ORDB1A3PE1500::
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* ORDB1A3PE1500::
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* ML501::
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* ML501::
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* Generic Designs::
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* Software::
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* Software::
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* GNU Free Documentation License:: The license for this documentation
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* GNU Free Documentation License:: The license for this documentation
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* Index::
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* Index::
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@end menu
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@end menu
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Turn off processor monitor's execution trace generation. This helps speed up the simulation (less time writing to files) and avoids creating very large execution logs (in the GBs) for very long simulations.
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Turn off processor monitor's execution trace generation. This helps speed up the simulation (less time writing to files) and avoids creating very large execution logs (in the GBs) for very long simulations.
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@item SIMULATOR
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@item SIMULATOR
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Specify simulator to use. Default is Icarus Verilog, can be set to @code{modelsim} to use Mentor Graphics' Modelsim. No others are supported right now.
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Specify simulator to use. Default is Icarus Verilog, can be set to @code{modelsim} to use Mentor Graphics' Modelsim. No others are supported right now.
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@item MGC_NO_VOPT
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When using Modelsim (specifying @code{SIMULATOR=modelsim}), if the version does not include the individual @code{vopt} executable, specify @code{MGC_NO_VOPT=1} when compiling.
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@end table
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@end table
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@node Reference Design Cycle Accurate
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@node Reference Design Cycle Accurate
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@subsection Cycle Accurate
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@subsection Cycle Accurate
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@cindex cycle accurate simulation of reference design
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@cindex cycle accurate simulation of reference design
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@subheading Running Cycle Accurate Regression Test
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@subheading Running Cycle Accurate Regression Test
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If both UART and debug interface are connected via the ORSoC USB debugger, this ultimately ends up witht he first 2 pins on the right column of J4 as RX/TX for the UART then the JTAG TDO, TDI, TMS and TCK in succession down the right column of J4.
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If both UART and debug interface are connected via the ORSoC USB debugger, this ultimately ends up witht he first 2 pins on the right column of J4 as RX/TX for the UART then the JTAG TDO, TDI, TMS and TCK in succession down the right column of J4.
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See the ML501 schematic (http://www.xilinx.com/support/documentation/boards_and_kits/ml501_20061010_bw.pdf) for more details on these headers, and refer to the pinouts in the ML501 UCF, in the board's @code{backend/par/bin/ml501.ucf} file.
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See the ML501 schematic (http://www.xilinx.com/support/documentation/boards_and_kits/ml501_20061010_bw.pdf) for more details on these headers, and refer to the pinouts in the ML501 UCF, in the board's @code{backend/par/bin/ml501.ucf} file.
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@c ****************************************************************************
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@c Generic Design build chapter
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@c ****************************************************************************
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@node Generic
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@chapter Generic
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@cindex Generic design information
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@menu
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* Overview::
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@end menu
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@node Generic Build Overview
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@section Overview
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The paths under @code{boards/generic} contain designs similar to the reference design, in that they are not technology specific, and used for development of certain features of the processor, or peripherals.
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An example is the fault tolerance testing build, in @code{boards/generic/ft}, which implements some custom modules in the testbench and ORPSoC top level design, and is in general a very minimal system just for testing.
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Additional builds, testing certain parts of the technology, can be developed here.
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@c ****************************************************************************
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@c ****************************************************************************
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@c Software section
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@c Software section
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@c ****************************************************************************
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@c ****************************************************************************
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