| Line 605... |
Line 605... |
RTL, gatelevel simulation: Mentor Graphics' Modelsim
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RTL, gatelevel simulation: Mentor Graphics' Modelsim
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Synthesis: Synopsys Synplify (included in Actel Libero Suite)
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Synthesis: Synopsys Synplify (included in Actel Libero Suite)
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Backend: Actel Designer (included in Actel Libero Suite)
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Backend: Actel Designer (included in Actel Libero Suite)
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Programming: Actel FlashPRO (included in Actel Libero Suite)
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Programming: Actel FlashPRO (included in Actel Libero Suite)
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This has been developed with Libero v8.6 for Linux.
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This has been tested with with Libero v8.6 and v9.0sp1 under Ubuntu Linux.
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@node ORDB1A3PE1500 Debug Tools
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@node ORDB1A3PE1500 Debug Tools
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@subsubsection Debug Tools
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@subsubsection Debug Tools
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@cindex Debug tools required ORDB1A3PE1500
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@cindex Debug tools required ORDB1A3PE1500
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| Line 735... |
Line 735... |
@kbd{make all}
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@kbd{make all}
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@end example
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@end example
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This will create a @code{.adb} file in the same path.
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This will create a @code{.adb} file in the same path.
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All steps, up to programming file generation are done here. This is mainly a licensing thing (free licenses for Libero under Linux @emph{do not} allow programming file generation - they do, however, under Windows.)
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All steps, up to and including programming file generation are done here. FPGA device programming must be done using the programming FlashPro tool under Windows if using a free license.
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@node ORDB1A3PE1500 Place and route options
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@node ORDB1A3PE1500 Place and route options
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@subsubsection Options
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@subsubsection Options
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Most of the design's parameters are determined by processing the @code{orpsoc-defines.v} file and determining, for example, the frequency of the clocks entering the design.
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Most of the design's parameters are determined by processing the @code{orpsoc-defines.v} file and extracting, for example, the frequency of the clocks entering the design.
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The following can be passed as environment variables when running @kbd{make all}.
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The following can be passed as environment variables when running @kbd{make all}.
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@table @code
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@table @code
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| Line 999... |
Line 999... |
RTL, gatelevel simulation: Mentor Graphics' Modelsim
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RTL, gatelevel simulation: Mentor Graphics' Modelsim
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Synthesis: XST (from Xilinx ISE)
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Synthesis: XST (from Xilinx ISE)
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Backend: ngdbuild/map/par/bitgen/promgen, etc. (from Xilinx ISE)
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Backend: ngdbuild/map/par/bitgen/promgen, etc. (from Xilinx ISE)
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Programming: iMPACT (from Xilinx ISE)
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Programming: iMPACT (from Xilinx ISE)
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This has been developed with Xilinx ISE 11.1 under Linux.
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This has been tested with Xilinx ISE 11.1 under Ubuntu Linux.
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@node ML501 Debug Tools
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@node ML501 Debug Tools
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@subsubsection Debug Tools
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@subsubsection Debug Tools
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@cindex Debug tools required ML501
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@cindex Debug tools required ML501
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