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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [arbiter/] [arbiter_bytebus.v] - Diff between revs 361 and 506

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Rev 361 Rev 506
Line 73... Line 73...
   wbs0_bte_i,
   wbs0_bte_i,
   wbs0_dat_o,
   wbs0_dat_o,
   wbs0_ack_o,
   wbs0_ack_o,
   wbs0_err_o,
   wbs0_err_o,
   wbs0_rty_o,
   wbs0_rty_o,
/*
 
   // Slave two
 
   // Wishbone Slave interface
 
   wbs1_adr_i,
 
   wbs1_dat_i,
 
   wbs1_we_i,
 
   wbs1_cyc_i,
 
   wbs1_stb_i,
 
   wbs1_cti_i,
 
   wbs1_bte_i,
 
   wbs1_dat_o,
 
   wbs1_ack_o,
 
   wbs1_err_o,
 
   wbs1_rty_o,
 
 
 
 
   // Slave two
 
   // Wishbone Slave interface
 
   wbs1_adr_i,
 
   wbs1_dat_i,
 
   wbs1_we_i,
 
   wbs1_cyc_i,
 
   wbs1_stb_i,
 
   wbs1_cti_i,
 
   wbs1_bte_i,
 
   wbs1_dat_o,
 
   wbs1_ack_o,
 
   wbs1_err_o,
 
   wbs1_rty_o,
 
/*
   // Slave three
   // Slave three
   // Wishbone Slave interface
   // Wishbone Slave interface
   wbs2_adr_i,
   wbs2_adr_i,
   wbs2_dat_i,
   wbs2_dat_i,
   wbs2_we_i,
   wbs2_we_i,
Line 418... Line 418...
   input [wbs_dat_width-1:0]  wbs0_dat_o;
   input [wbs_dat_width-1:0]  wbs0_dat_o;
   input                     wbs0_ack_o;
   input                     wbs0_ack_o;
   input                     wbs0_err_o;
   input                     wbs0_err_o;
   input                     wbs0_rty_o;
   input                     wbs0_rty_o;
 
 
/*
 
   // Wishbone Slave interface
 
   output [wb_adr_width-1:0] wbs1_adr_i;
 
   output [wbs_dat_width-1:0] wbs1_dat_i;
 
   output                    wbs1_we_i;
 
   output                    wbs1_cyc_i;
 
   output                    wbs1_stb_i;
 
   output [2:0]              wbs1_cti_i;
 
   output [1:0]              wbs1_bte_i;
 
   input [wbs_dat_width-1:0]  wbs1_dat_o;
 
   input                     wbs1_ack_o;
 
   input                     wbs1_err_o;
 
   input                     wbs1_rty_o;
 
 
 
 
   // Wishbone Slave interface
 
   output [wb_adr_width-1:0] wbs1_adr_i;
 
   output [wbs_dat_width-1:0] wbs1_dat_i;
 
   output                    wbs1_we_i;
 
   output                    wbs1_cyc_i;
 
   output                    wbs1_stb_i;
 
   output [2:0]       wbs1_cti_i;
 
   output [1:0]       wbs1_bte_i;
 
   input [wbs_dat_width-1:0]  wbs1_dat_o;
 
   input                     wbs1_ack_o;
 
   input                     wbs1_err_o;
 
   input                     wbs1_rty_o;
 
 
 
/*
   // Wishbone Slave interface
   // Wishbone Slave interface
   output [wb_adr_width-1:0] wbs2_adr_i;
   output [wb_adr_width-1:0] wbs2_adr_i;
   output [wbs_dat_width-1:0] wbs2_dat_i;
   output [wbs_dat_width-1:0] wbs2_dat_i;
   output                    wbs2_we_i;
   output                    wbs2_we_i;
   output                    wbs2_cyc_i;
   output                    wbs2_cyc_i;
Line 786... Line 786...
   wire                      wbs_err_o_mux_i [0:wb_num_slaves-1];
   wire                      wbs_err_o_mux_i [0:wb_num_slaves-1];
   wire                      wbs_rty_o_mux_i [0:wb_num_slaves-1];
   wire                      wbs_rty_o_mux_i [0:wb_num_slaves-1];
 
 
   // Slave selects
   // Slave selects
   assign wb_slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave0_adr;
   assign wb_slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave0_adr;
 
   assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
   /*
   /*
   assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
 
   assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr;
   assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr;
   assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr;
   assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr;
   assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr;
   assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr;
   assign wb_slave_sel[5] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave5_adr;
   assign wb_slave_sel[5] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave5_adr;
   assign wb_slave_sel[6] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave6_adr;
   assign wb_slave_sel[6] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave6_adr;
Line 824... Line 824...
   assign wbs_dat_o_mux_i[0] = wbs0_dat_o;
   assign wbs_dat_o_mux_i[0] = wbs0_dat_o;
   assign wbs_ack_o_mux_i[0] = wbs0_ack_o & wb_slave_sel[0];
   assign wbs_ack_o_mux_i[0] = wbs0_ack_o & wb_slave_sel[0];
   assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel[0];
   assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel[0];
   assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel[0];
   assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel[0];
 
 
   /*
 
   // Slave 1 inputs
 
   assign wbs1_adr_i = wbm_adr_o;
 
   assign wbs1_dat_i = wbm_dat_o;
 
   assign wbs1_cyc_i = wbm_cyc_o & wb_slave_sel[1];
 
   assign wbs1_stb_i = wbm_stb_o & wb_slave_sel[1];
 
   assign  wbs1_we_i =  wbm_we_o;
 
   assign wbs1_cti_i = wbm_cti_o;
 
   assign wbs1_bte_i = wbm_bte_o;
 
   assign wbs_dat_o_mux_i[1] = wbs1_dat_o;
 
   assign wbs_ack_o_mux_i[1] = wbs1_ack_o & wb_slave_sel[1];
 
   assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel[1];
 
   assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel[1];
 
 
 
 
   // Slave 1 inputs
 
   assign wbs1_adr_i = wbm_adr_o;
 
   assign wbs1_dat_i = wbm_dat_o;
 
   assign wbs1_cyc_i = wbm_cyc_o & wb_slave_sel[1];
 
   assign wbs1_stb_i = wbm_stb_o & wb_slave_sel[1];
 
   assign  wbs1_we_i =  wbm_we_o;
 
   assign wbs1_cti_i = wbm_cti_o;
 
   assign wbs1_bte_i = wbm_bte_o;
 
   assign wbs_dat_o_mux_i[1] = wbs1_dat_o;
 
   assign wbs_ack_o_mux_i[1] = wbs1_ack_o & wb_slave_sel[1];
 
   assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel[1];
 
   assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel[1];
 
 
 
   /*
   // Slave 2 inputs
   // Slave 2 inputs
   assign wbs2_adr_i = wbm_adr_o;
   assign wbs2_adr_i = wbm_adr_o;
   assign wbs2_dat_i = wbm_dat_o;
   assign wbs2_dat_i = wbm_dat_o;
   assign wbs2_cyc_i = wbm_cyc_o & wb_slave_sel[2];
   assign wbs2_cyc_i = wbm_cyc_o & wb_slave_sel[2];
   assign wbs2_stb_i = wbm_stb_o & wb_slave_sel[2];
   assign wbs2_stb_i = wbm_stb_o & wb_slave_sel[2];
Line 1093... Line 1093...
 
 
 
 
 
 
   // Master out mux from slave in data
   // Master out mux from slave in data
   assign wbm_dat_byte_i = wb_slave_sel[0] ? wbs_dat_o_mux_i[0] :
   assign wbm_dat_byte_i = wb_slave_sel[0] ? wbs_dat_o_mux_i[0] :
/*
                      wb_slave_sel[1] ? wbs_dat_o_mux_i[1] :
                      wb_slave_sel[1] ? wbs_dat_o_mux_i[1] :
/*                    wb_slave_sel[2] ? wbs_dat_o_mux_i[2] :
                      wb_slave_sel[2] ? wbs_dat_o_mux_i[2] :
 
                      wb_slave_sel[3] ? wbs_dat_o_mux_i[3] :
                      wb_slave_sel[3] ? wbs_dat_o_mux_i[3] :
                      wb_slave_sel[4] ? wbs_dat_o_mux_i[4] :
                      wb_slave_sel[4] ? wbs_dat_o_mux_i[4] :
                      wb_slave_sel[5] ? wbs_dat_o_mux_i[5] :
                      wb_slave_sel[5] ? wbs_dat_o_mux_i[5] :
                      wb_slave_sel[6] ? wbs_dat_o_mux_i[6] :
                      wb_slave_sel[6] ? wbs_dat_o_mux_i[6] :
                      wb_slave_sel[7] ? wbs_dat_o_mux_i[7] :
                      wb_slave_sel[7] ? wbs_dat_o_mux_i[7] :
Line 1116... Line 1115...
                      wb_slave_sel[18] ? wbs_dat_o_mux_i[18] :
                      wb_slave_sel[18] ? wbs_dat_o_mux_i[18] :
                      wb_slave_sel[19] ? wbs_dat_o_mux_i[19] :
                      wb_slave_sel[19] ? wbs_dat_o_mux_i[19] :
*/
*/
                      wbs_dat_o_mux_i[0];
                      wbs_dat_o_mux_i[0];
   // Master out acks, or together
   // Master out acks, or together
   assign wbm_ack_i = wbs_ack_o_mux_i[0]  /* |
   assign wbm_ack_i = wbs_ack_o_mux_i[0]  |
                      wbs_ack_o_mux_i[1]  |
                      wbs_ack_o_mux_i[1]  /* |
                      wbs_ack_o_mux_i[2]  |
                      wbs_ack_o_mux_i[2]  |
                      wbs_ack_o_mux_i[3]  |
                      wbs_ack_o_mux_i[3]  |
                      wbs_ack_o_mux_i[4]  |
                      wbs_ack_o_mux_i[4]  |
                      wbs_ack_o_mux_i[5]  |
                      wbs_ack_o_mux_i[5]  |
                      wbs_ack_o_mux_i[6]  |
                      wbs_ack_o_mux_i[6]  |
Line 1140... Line 1139...
                      wbs_ack_o_mux_i[19]
                      wbs_ack_o_mux_i[19]
                      */
                      */
                      ;
                      ;
 
 
 
 
   assign wbm_err_i = wbs_err_o_mux_i[0] |/*
   assign wbm_err_i = wbs_err_o_mux_i[0] |
                      wbs_err_o_mux_i[1] |
                      wbs_err_o_mux_i[1] |/*
                      wbs_err_o_mux_i[2] |
                      wbs_err_o_mux_i[2] |
                      wbs_err_o_mux_i[3] |
                      wbs_err_o_mux_i[3] |
                      wbs_err_o_mux_i[4] |
                      wbs_err_o_mux_i[4] |
                      wbs_err_o_mux_i[5] |
                      wbs_err_o_mux_i[5] |
                      wbs_err_o_mux_i[6] |
                      wbs_err_o_mux_i[6] |
Line 1164... Line 1163...
                      wbs_err_o_mux_i[19] |
                      wbs_err_o_mux_i[19] |
                                       */
                                       */
                      watchdog_err  ;
                      watchdog_err  ;
 
 
 
 
   assign wbm_rty_i = wbs_rty_o_mux_i[0]  /*|
   assign wbm_rty_i = wbs_rty_o_mux_i[0]  |
                      wbs_rty_o_mux_i[1]  |
                      wbs_rty_o_mux_i[1]  /*|
                      wbs_rty_o_mux_i[2]  |
                      wbs_rty_o_mux_i[2]  |
                      wbs_rty_o_mux_i[3]  |
                      wbs_rty_o_mux_i[3]  |
                      wbs_rty_o_mux_i[4]  |
                      wbs_rty_o_mux_i[4]  |
                      wbs_rty_o_mux_i[5]  |
                      wbs_rty_o_mux_i[5]  |
                      wbs_rty_o_mux_i[6]  |
                      wbs_rty_o_mux_i[6]  |

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