| Line 73... |
Line 73... |
wbs0_bte_i,
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wbs0_bte_i,
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wbs0_dat_o,
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wbs0_dat_o,
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wbs0_ack_o,
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wbs0_ack_o,
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wbs0_err_o,
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wbs0_err_o,
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wbs0_rty_o,
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wbs0_rty_o,
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/*
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// Slave two
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// Wishbone Slave interface
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wbs1_adr_i,
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wbs1_dat_i,
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wbs1_we_i,
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wbs1_cyc_i,
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wbs1_stb_i,
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wbs1_cti_i,
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wbs1_bte_i,
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wbs1_dat_o,
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wbs1_ack_o,
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wbs1_err_o,
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wbs1_rty_o,
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// Slave two
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// Wishbone Slave interface
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wbs1_adr_i,
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wbs1_dat_i,
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wbs1_we_i,
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wbs1_cyc_i,
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wbs1_stb_i,
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wbs1_cti_i,
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wbs1_bte_i,
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wbs1_dat_o,
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wbs1_ack_o,
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wbs1_err_o,
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wbs1_rty_o,
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/*
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// Slave three
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// Slave three
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// Wishbone Slave interface
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// Wishbone Slave interface
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wbs2_adr_i,
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wbs2_adr_i,
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wbs2_dat_i,
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wbs2_dat_i,
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wbs2_we_i,
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wbs2_we_i,
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| Line 418... |
Line 418... |
input [wbs_dat_width-1:0] wbs0_dat_o;
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input [wbs_dat_width-1:0] wbs0_dat_o;
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input wbs0_ack_o;
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input wbs0_ack_o;
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input wbs0_err_o;
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input wbs0_err_o;
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input wbs0_rty_o;
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input wbs0_rty_o;
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/*
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// Wishbone Slave interface
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output [wb_adr_width-1:0] wbs1_adr_i;
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output [wbs_dat_width-1:0] wbs1_dat_i;
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output wbs1_we_i;
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output wbs1_cyc_i;
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output wbs1_stb_i;
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output [2:0] wbs1_cti_i;
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output [1:0] wbs1_bte_i;
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input [wbs_dat_width-1:0] wbs1_dat_o;
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input wbs1_ack_o;
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input wbs1_err_o;
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input wbs1_rty_o;
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// Wishbone Slave interface
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output [wb_adr_width-1:0] wbs1_adr_i;
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output [wbs_dat_width-1:0] wbs1_dat_i;
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output wbs1_we_i;
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output wbs1_cyc_i;
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output wbs1_stb_i;
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output [2:0] wbs1_cti_i;
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output [1:0] wbs1_bte_i;
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input [wbs_dat_width-1:0] wbs1_dat_o;
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input wbs1_ack_o;
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input wbs1_err_o;
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input wbs1_rty_o;
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/*
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// Wishbone Slave interface
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// Wishbone Slave interface
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output [wb_adr_width-1:0] wbs2_adr_i;
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output [wb_adr_width-1:0] wbs2_adr_i;
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output [wbs_dat_width-1:0] wbs2_dat_i;
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output [wbs_dat_width-1:0] wbs2_dat_i;
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output wbs2_we_i;
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output wbs2_we_i;
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output wbs2_cyc_i;
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output wbs2_cyc_i;
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| Line 786... |
Line 786... |
wire wbs_err_o_mux_i [0:wb_num_slaves-1];
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wire wbs_err_o_mux_i [0:wb_num_slaves-1];
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wire wbs_rty_o_mux_i [0:wb_num_slaves-1];
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wire wbs_rty_o_mux_i [0:wb_num_slaves-1];
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// Slave selects
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// Slave selects
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assign wb_slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave0_adr;
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assign wb_slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave0_adr;
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assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
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/*
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/*
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assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
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assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr;
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assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr;
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assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr;
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assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr;
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assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr;
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assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr;
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assign wb_slave_sel[5] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave5_adr;
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assign wb_slave_sel[5] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave5_adr;
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assign wb_slave_sel[6] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave6_adr;
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assign wb_slave_sel[6] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave6_adr;
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| Line 824... |
Line 824... |
assign wbs_dat_o_mux_i[0] = wbs0_dat_o;
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assign wbs_dat_o_mux_i[0] = wbs0_dat_o;
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assign wbs_ack_o_mux_i[0] = wbs0_ack_o & wb_slave_sel[0];
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assign wbs_ack_o_mux_i[0] = wbs0_ack_o & wb_slave_sel[0];
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assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel[0];
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assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel[0];
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assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel[0];
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assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel[0];
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/*
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// Slave 1 inputs
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assign wbs1_adr_i = wbm_adr_o;
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assign wbs1_dat_i = wbm_dat_o;
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assign wbs1_cyc_i = wbm_cyc_o & wb_slave_sel[1];
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assign wbs1_stb_i = wbm_stb_o & wb_slave_sel[1];
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assign wbs1_we_i = wbm_we_o;
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assign wbs1_cti_i = wbm_cti_o;
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assign wbs1_bte_i = wbm_bte_o;
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assign wbs_dat_o_mux_i[1] = wbs1_dat_o;
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assign wbs_ack_o_mux_i[1] = wbs1_ack_o & wb_slave_sel[1];
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assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel[1];
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assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel[1];
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// Slave 1 inputs
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assign wbs1_adr_i = wbm_adr_o;
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assign wbs1_dat_i = wbm_dat_o;
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assign wbs1_cyc_i = wbm_cyc_o & wb_slave_sel[1];
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assign wbs1_stb_i = wbm_stb_o & wb_slave_sel[1];
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assign wbs1_we_i = wbm_we_o;
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assign wbs1_cti_i = wbm_cti_o;
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assign wbs1_bte_i = wbm_bte_o;
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assign wbs_dat_o_mux_i[1] = wbs1_dat_o;
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assign wbs_ack_o_mux_i[1] = wbs1_ack_o & wb_slave_sel[1];
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assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel[1];
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assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel[1];
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/*
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// Slave 2 inputs
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// Slave 2 inputs
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assign wbs2_adr_i = wbm_adr_o;
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assign wbs2_adr_i = wbm_adr_o;
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assign wbs2_dat_i = wbm_dat_o;
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assign wbs2_dat_i = wbm_dat_o;
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assign wbs2_cyc_i = wbm_cyc_o & wb_slave_sel[2];
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assign wbs2_cyc_i = wbm_cyc_o & wb_slave_sel[2];
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assign wbs2_stb_i = wbm_stb_o & wb_slave_sel[2];
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assign wbs2_stb_i = wbm_stb_o & wb_slave_sel[2];
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| Line 1093... |
Line 1093... |
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// Master out mux from slave in data
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// Master out mux from slave in data
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assign wbm_dat_byte_i = wb_slave_sel[0] ? wbs_dat_o_mux_i[0] :
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assign wbm_dat_byte_i = wb_slave_sel[0] ? wbs_dat_o_mux_i[0] :
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/*
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wb_slave_sel[1] ? wbs_dat_o_mux_i[1] :
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wb_slave_sel[1] ? wbs_dat_o_mux_i[1] :
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/* wb_slave_sel[2] ? wbs_dat_o_mux_i[2] :
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wb_slave_sel[2] ? wbs_dat_o_mux_i[2] :
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wb_slave_sel[3] ? wbs_dat_o_mux_i[3] :
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wb_slave_sel[3] ? wbs_dat_o_mux_i[3] :
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wb_slave_sel[4] ? wbs_dat_o_mux_i[4] :
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wb_slave_sel[4] ? wbs_dat_o_mux_i[4] :
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wb_slave_sel[5] ? wbs_dat_o_mux_i[5] :
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wb_slave_sel[5] ? wbs_dat_o_mux_i[5] :
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wb_slave_sel[6] ? wbs_dat_o_mux_i[6] :
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wb_slave_sel[6] ? wbs_dat_o_mux_i[6] :
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wb_slave_sel[7] ? wbs_dat_o_mux_i[7] :
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wb_slave_sel[7] ? wbs_dat_o_mux_i[7] :
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| Line 1116... |
Line 1115... |
wb_slave_sel[18] ? wbs_dat_o_mux_i[18] :
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wb_slave_sel[18] ? wbs_dat_o_mux_i[18] :
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wb_slave_sel[19] ? wbs_dat_o_mux_i[19] :
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wb_slave_sel[19] ? wbs_dat_o_mux_i[19] :
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*/
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*/
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wbs_dat_o_mux_i[0];
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wbs_dat_o_mux_i[0];
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// Master out acks, or together
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// Master out acks, or together
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assign wbm_ack_i = wbs_ack_o_mux_i[0] /* |
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assign wbm_ack_i = wbs_ack_o_mux_i[0] |
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wbs_ack_o_mux_i[1] |
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wbs_ack_o_mux_i[1] /* |
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wbs_ack_o_mux_i[2] |
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wbs_ack_o_mux_i[2] |
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wbs_ack_o_mux_i[3] |
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wbs_ack_o_mux_i[3] |
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wbs_ack_o_mux_i[4] |
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wbs_ack_o_mux_i[4] |
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wbs_ack_o_mux_i[5] |
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wbs_ack_o_mux_i[5] |
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wbs_ack_o_mux_i[6] |
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wbs_ack_o_mux_i[6] |
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| Line 1140... |
Line 1139... |
wbs_ack_o_mux_i[19]
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wbs_ack_o_mux_i[19]
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*/
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*/
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;
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;
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assign wbm_err_i = wbs_err_o_mux_i[0] |/*
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assign wbm_err_i = wbs_err_o_mux_i[0] |
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wbs_err_o_mux_i[1] |
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wbs_err_o_mux_i[1] |/*
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wbs_err_o_mux_i[2] |
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wbs_err_o_mux_i[2] |
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wbs_err_o_mux_i[3] |
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wbs_err_o_mux_i[3] |
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wbs_err_o_mux_i[4] |
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wbs_err_o_mux_i[4] |
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wbs_err_o_mux_i[5] |
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wbs_err_o_mux_i[5] |
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wbs_err_o_mux_i[6] |
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wbs_err_o_mux_i[6] |
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| Line 1164... |
Line 1163... |
wbs_err_o_mux_i[19] |
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wbs_err_o_mux_i[19] |
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*/
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*/
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watchdog_err ;
|
watchdog_err ;
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assign wbm_rty_i = wbs_rty_o_mux_i[0] /*|
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assign wbm_rty_i = wbs_rty_o_mux_i[0] |
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wbs_rty_o_mux_i[1] |
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wbs_rty_o_mux_i[1] /*|
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wbs_rty_o_mux_i[2] |
|
wbs_rty_o_mux_i[2] |
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wbs_rty_o_mux_i[3] |
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wbs_rty_o_mux_i[3] |
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wbs_rty_o_mux_i[4] |
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wbs_rty_o_mux_i[4] |
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wbs_rty_o_mux_i[5] |
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wbs_rty_o_mux_i[5] |
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wbs_rty_o_mux_i[6] |
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wbs_rty_o_mux_i[6] |
|
