URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [clkgen/] [clkgen.v] - Diff between revs 361 and 362

Rev 361	Rev 362
Line 89...	Line 89...
`// Declare synchronous reset wires here`	`// Declare synchronous reset wires here`
`//`	`//`

`// An active-low synchronous reset signal (usually a PLL lock signal)`	`// An active-low synchronous reset signal (usually a PLL lock signal)`
`wire sync_rst_n;`	`wire sync_rst_n;`
	`assign sync_rst_n = async_rst_n; // Pretend it's somehow synchronous now`

`// An active-low synchronous reset from ethernet PLL`
`wire sync_eth_rst_n;`

`// Here we just assign "board" clock (really test) to wishbone clock`	`// Here we just assign "board" clock (really test) to wishbone clock`
`assign wb_clk_o = clk_pad_i;`	`assign wb_clk_o = clk_pad_i;`

`//`	`//`